Three questions about timing

[mImoto]

Timing questions??

Dear all,

I am a bit new with timing problems and I would like to ask you three
questions. So, here we go:

First question:

In my design I have to control /CS and /RD signals. The specifications says
that the /RD signal has a setup time to the asserting of /CS of 0ns (/CS
should be asserted at least 0ns before /RD is asserted) and Thold of /CS to
/RD also is 0ns ( the /CS should be de-asserted after the /RD is
de-asserted). In the TimingQuestion.jpg you can see that if in my state machine I assert
and de-assert /CS a clock cicle before and after /RD then the timings are
always correct. In the case of signal /CS1 I assert and de-assert /CS1 in
the same cicle as /RD, then it seems that could be possible that timings are
not met. I think that doing the first option adds delay and I would like to
know how you experts do these, I mean, would you change /CS in the same
cicle as /RD or not (signal /CS1 or signal /CS in the .bmp) ?.

second similar question:

I have a bus data and the specifications say that I must release the data at
least 0ns before rising (de-asserting) the /ACK signal. Should I also
release the data bus and in the next cicle rise the /ACK or it is better to
do in the same cicle to not add delays (like signal /ACK1 in the TimingQuestion.jpg)?.

third question:

Last Question:

In my State Machine I would like to go from STATE0 to STATE1 when an
asynchronous signal /DS goes low (I mean with the falling edge of /DS). I
have thought to use this EdgeDetectingSynchronizer.jpg and pass to STATE1 when /DS2 is '0' and OUTPUT is '1'. Would that be correct to synchronize the /DS asyncronous signal (in my case VME signal)?.


Thanks a lot and best regards,

mimoto

 

[tom_hanks]

Re: Timing questions??

1.
basically it depend upon the design..
if its ROM kind of thing the u can assert and deassert both signal on same cycle..
but if its some FIFO or logic then assert first /CS n then /RD
similarliy deassert /RD signal 1st then /CS...so ur operation will be with referece to /cs..

2.
it look bit confusing..8O
usually if data bus is relesed by design, then in return it get acknoldege signal as an input..
i guess u have to sample the ack as a received flag..means u can send next data only after
receving this signal..

3.
i didnt get ur question..

tom

 

[pplu]

Re: Timing questions??

3. This is a circuit to detect the rising edge. To detect the falling edge,
the inputs to the gate should be swapped, thus a pulse on the output
indicates the falling edge of /DS and you can move the state. This circuit
will introduce delay, and it would be correct if other signals are happy
with this delay.

 

[tut]

Re: Timing questions??

In reference to your VME question, u can check the level of DS line at the rising or falling edge(whichever?) of the clock u r using.. upon seeing it as a low signal , u can jump to the next state...