That's sort of a recursive solution, since the object is to
"design" (or simply acquire) the encoder logic for a flash
ADC's guts. And of course the speed of a high impedance
analog scheme would not really support the applications
that favor flash ADCs.
This logic may also be referred to as "priority encoder"
(from back before flash ADCs were the primary use of it).
Casual searching yields designs only up to 4 bits. I know
of 8-bit flash designs (which belong to somebody, and
won't be posted publicly) and cascadable priority encoders
in the 4-bit range did exist.
Because signal range is low and VT scatter probably high,
some thought wants to be given to code nonidealities
and how the encoder deals with them (e.g. a comparator
that's way offset, could give you a "bubble" in the bit
field that might drive some combinatorial logic styles crazy
if they don't merely work off the highest "set" bit. Like
1111111111111101000000000000000 is an invalid code
for the presumption of thermometer, one and only one
1-0 boundary.
A scheme such as one rank of "suppress the lesser"
logic (creating a single high bit in a field of zeroes,
which makes a dandy decode) followed by a small ROM
could be efficient. I have seen some very compact but
funny looking pass-transistor logic as well (but this is
not a style I favor, for speed and timing consistency).