Thermal vias in a DPAK pad is OK?

[treez]

Hello,

Is it allright to put thermal vias in the DPAK drain pad so that i can transport heat away to some copper on the opposite surface.?

I have heard somewhere that its wrong, but in truth, cant see why it should be a problem?

 

[lhademmor]

Cause You are heating up under the soldermask ink on opposite surface. 2 ways to easely aviod this is to "open" in soldermask on opposite site or fill the via hole, the last one is very well known and used, as qfn packages has same problem .

But in the end it depends on the mounting fabric/assembly house

 

[treez]

thamks... i thought the fact that there's soldermask on the bottom thermal spreading copper is irrelevant, i mean, if hot solder goes through the via, then it will just melt the soldermask ink, harmlessly?


.....also, why would solder want to "wick" down a via?.......solder only wicks towards hotter surfaces than the surface its on........and the bottom surface would not be hotter, surely?

 

[Alan0354]

If it is for heat transfer, you don't want thermal vias at all. The thermal is to cut groove between the pads and the copper plane, leaving only 4 thin traces connecting it. This is to prevent good heat transfer from the pads to the plane. The whole thing about thermal on vias is to isolate the heat from the pads to travel to the copper plane. That is for soldering purpose. If you don't have a thermal, the heat from the soldering iron get dissipated out onto the plane, that makes it hard to solder. But for your case, you use the via to transfer heat, the last thing you want is to put thermal to block the heat transfer from the via to the copper plane.

 

[andre_luis]

If soldering is done by stove, I guess thermal vias is not an issue.
The problem exists if you espect perform further maintenance, due to heat will be drawn more accentuated, reducing thermal gradient.


+++

 

[Mattylad]

Yes it IS ok to put vias in your DPAK large drain pad, it is very common to do this, although they should not have any thermal relief (which is what I think Alan is referring to) and they should not have solder paste on them as it does wick down the via holes.

If a manufactured board, and plenty of them then they should really be "plugged", smaller hand assembled prototypes should be fine without plugging.

As well as that your solder paste pad shape should not really cover the same size as the pad as that outs too much solder on the pad and can lead to solder balling etc, most prefer to reduce it to about 70% by making a matrix of shapes on the solder paste layer, if you are having solder vias you can make an anulus ring of solder paste around them to prevent any solder going down the hole.

If this component is to be used once then you can add vias in the single job, if it is likely to be used a lot then it may be better to do this in the component, add the vias in the component in the library - but not as vias but as pads.

You have not said which PCB package you are using, if using CADSTAR here is a guide on how to do it.

 

[FvM]

As well as that your solder paste pad shape should not really cover the same size as the pad as that outs too much solder on the pad and can lead to solder balling etc, most prefer to reduce it to about 70% by making a matrix of shapes on the solder paste layer, if you are having solder vias you can make an anulus ring of solder paste around them to prevent any solder going down the hole.

Solder will spread all over the open pad area, not caring much about the stencil structure. The linked Cadstar thermal via guideline is in contrast talking about solder resist annular rings to prevent solder wicking.

I have tried similar constructs some years ago and found that some PCB manufacturers apparently have difficulties to reproduce clean solder mask structures in this situation. I got solder resist residuals on the remaining pad area that has to be cleaned manually. Due to this uncertain results we decided not to further pursue this method.

For high performance PCB, we generally go for metallized plugging (via in pad), because the surcharge is pretty much compensated by the increase in wiring density. For simple PCBs, small (e.g. 0.3 mm finished diameter) open thermal vias with a small solder resist opening (slightly above drill diameter) on the bottom side has turned out applicable. Some assembly service providers mentioned a reservation, that chip scale package ICs (CSP, QFN) might be "pulled down" by solder wicking, causing shorts between the downside pads. Although I didn't yet observe this problem, the consideration sounds plausible. But the problem definitely doesn't apply to packages like DPAK, MSOP or QFP with thermal pad.

 

[Alan0354]

Yes it IS ok to put vias in your DPAK large drain pad, it is very common to do this, although they should not have any thermal relief (which is what I think Alan is referring to) and they should not have solder paste on them as it does wick down the via holes.

Exactly. I did that many times, I put solder mask on the whole patch so I can use a big iron to solder the transistor/whatever on to it.

 

[marce]

IPC-7093 and numerousIC manufacturers guidline on thesetype of devices.
As FvM mentioned plugged vias is the best option but not always available due to cost. Done loads of designs with these features where via plugging was not an option, controlling the stencil and location of solder pastes helps and you can achieve a IPC-610 class 3 assembly without via plugging.

 

[treez]

Reference the thoughts on the thermal vias in the power pad "pulling" the fet out of line, and resulting in shorting, do you think this is a danger if we put vias in the pad of the AON6284 FET (DFN5X6 package)

DFN5X6 FET PACKAGE (AON6284 FET) datasheet
http://www.aosmd.com/res/data_sheets/AON6284.pdf

Here is the land pattern for the DFN5X6 package:
**broken link removed**

 

[FvM]

I don't expect soldering problems with this rather coarse SMT structures if you have 0.3 mm vias in the large pads.

 

[treez]

by "coarse" do you mean that putting vias in the pads is ok, but a little crude and unprofessional?

 

[FvM]

I think the sense is clear if you just read the words carefully. I said "coarse structures", which means that pad size and pad clearance is so large that you don't get easily solder shorts.

Open thermal vias are not generally a problem for professional designs.

 

[treez]

For simple PCBs, small (e.g. 0.3 mm finished diameter) open thermal vias with a small solder resist opening (slightly above drill diameter) on the bottom side has turned out applicable

..thanks, but how does having solder resist on the bottom side annulus help?
(presumably you mean the solder resist on the bottom side to just be an annulus sitting on the bottom side metal annulus of the thermal via?)

The problem with having solder resist on the bottom side annulus of a thermal via, is that in Eagle Pro if you put solder resist there, then you also end up with solder resist on the top side annulus of the thermal via, and of course, this is disastrous, because the top side is in the thermal pad of the power semiconductor, and we don't want solder resist in the pad.....so how, in Eagle Pro, does one get solder resist on only the bottom side annulus of the thermal via?

Also, when you say "0.3mm", do you infer that eg 0.4mm is too big a via drill hole and solder would wick away down it, causing an improper solder connection?

 

[FvM]

Is it true that Eagle has no option to make user specific via padstacks with e.g. different solder mask opening on top and bottom side? If so, some manual work in the postprocess like manipulating apertures may be required.

But in case of thermal vias, there's no need for different mask pads, because the component mask pad overlays the via pad and keeps the topside free from soldermask, whatever the via mask pad looks like.

I believe that via diameters above 0.3 mm aren't good for thermal vias, you can refer to other application notes and should collect your own experience.

Below a drawing of an open thermal via from an Amkor application note.

 

[D.A.(Tony)Stewart]

You ought to have the IPC-7351 pads libraries if you want a proper job.

1st you must decide on reflow or wave solder for each part affected. Many are different.

This site has the library for each CAD tool for sale.
https://www.pcblibraries.com/downloads/samples/EAGLE Sample Library.zip

The most common mistakes are design from nexperience that result in bad solder joints, EMI, thermal issues. Electrical skills are not enough.

 

[ftsolutions]

I don't put vias in the D2PAK pads. If I use vias for heat transfer on these type devices, I leave the pad "clean" to maximize the surface area that is in contact with and soldered to the device's tab. You don't want solder voids from poorly wicked solder, blowby, misaligned parts, etc. reducing your surface area and lowering thermal conductivity. I place vias around the outer edge of the pad, connected to the pad with VERY VERY short, wide copper traces to provide maximum distance/area for the dissipation of heat into another layer. As other have pointed out - it can be done (putting vias in the pad), but in my experience with some assembly shops, some can handle it better than others, even if a patterned soldermask is applied around the vias. And plugging vias does add some cost.

On parts like QFN, you really don't have much choice, but even there you should choose to not pack in too many vias and consider a patterned/cross hatch soldermask or use smaller diameter vias to avoid creating solder wicking issues (vias causing loss of solder between PCB pad and paddle on underside of the QFN part).