The VDD fluctuation of DAC.

[Question]

fluctuation in dac

I design a DAC, using current steering architecture. The base current source cell likes the picture below.

The bias voltage come from bandgap circuit. it is steady. But the VDD will have 5% to 10% fluctuation becaues of the source out of the chip. So the output current will change a lot by different VDD voltage.

How can I slove this problem? Please give me some advice. It is emergency!!

Thank you very much.

 

[xuel]

add big cap between biasp and vdd

 

[maxwellequ]

What do you mean by "The bias voltage come from bandgap circuit." -> Is is connected directly to VBG ? If yes, this is not the way it should be done. The bias voltage should be generated by a current mirror (the simpler solution is a transistor connected as a diode).

The current that goes to that diode connected transistor may be defined by the VBG and by a resistor.

Regards

 

[VVV]

If Vbias is kept constant with respect to Vdd, not with respect to GND, then your current will be constant and the DAC will work properly even with large Vdd variations.
So, use a precision series reference connected between Vdd and Vbias.

 

[Question]

What do you mean by "The bias voltage come from bandgap circuit." -> Is is connected directly to VBG ? If yes, this is not the way it should be done. The bias voltage should be generated by a current mirror (the simpler solution is a transistor connected as a diode).

The current that goes to that diode connected transistor may be defined by the VBG and by a resistor.

Regards

I do not understand your solution. Even the voltage come from bandgap circuit do
not connect to 'Vbias' directly. It connect to a current mirror then generate a
bias voltage. The current out of current mirror also respect to (VDD-VBG) that is
Vgs. When the VDD has variations the output of current mirror will change too.

Could you give me a circuit to explain your solution, thanks a lot.

And to my design, it is a voltage bias circuit, not crrent bias. I use Vgs to
generate current. I can not find out a way can make the Vgs constant, it is the
main problem.

 

[arsenal]

I design a DAC, using current steering architecture. The base current source cell likes the picture below.

The bias voltage come from bandgap circuit. it is steady. But the VDD will have 5% to 10% fluctuation becaues of the source out of the chip. So the output current
~~~~~~~~~~~~~~~
means what?
will change a lot by different VDD voltage.

How can I slove this problem? Please give me some advice. It is emergency!!

Thank you very much.

and i wanna know how u ensure the match of the steering currents? and the offset of the buffer?

 

[yeewong_su]

Use the current source gen from bandgap and not change with the power. Then mirror to the dac cell.

 

[lianming1]

good idea, but how you generate the current? and what do you mean by "not change with the power"?

 

[yeewong_su]

good idea, but how you generate the current? and what do you mean by "not change with the power"?

bandgap to generate the voltage to generate the current using the resistor
may be it' so easy

 

[lianming1]

but what i mean that the current has some disadvanges due to resistor,
I think it is not perfect

 

[andy1]

Try to use a spectrum analyzer and see the noise frequency spectrum of that Vdd node.

then try to add appropriate cap (that has Q at those noise frequencies).

Also add ferrite beads or power chokes.

 

[lmlee]

good, but the noise has some strange characters, you konw ,maybe it occure in certain time and certain enviroemnts.

 

[jiangwp]

I think the DAC use the scale for current, if the reference changes, the other scale current also change.

But maybe , the scale is not the same, so cause erro.

Maybe you can add a decouple capacitor on VDD.

 

[one9]

Try PMOS current mirror for bandgap generated current. Vgs keep constant since constant current, even VDD has variation.

Added after 1 minutes:

Try PMOS current mirror for bandgap generated current. Vgs keep constant since constant current, even VDD has variation.