The significance of wire load and speed grade

[rogger123]

wire load significance

during synthesis targeted at fpga's, when we choose the target device synopsys or say any tool gives us various options uch as wire load speed grade...
can any one explain the significance of wire load and speed grade

 

[eternal_nan]

wire load significance

Most FPGA synthesis tools dont allow you to choose a wire load model since it is useless (the wire lenths and loads in the fpga are well known) the speed grade option tells you roughly how fast your particular part is (due to process variation the results of the same design could be slower/faster after manufacturing). Wire load models are used by asic synthesis tools to estimate the R and C of wires connecting synthesized gates based on fanout and overall design size...

 

[galant]

Re: wire load significance

Wire load model is one of basic features of the synthesis and PKS tools now.