The Schematic input in QII problem

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Eiffel.Z

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Hi,
Now I design the module_A, define the output[15:0] Data_reg
then I design the 2 module, RAM0, and RAM1.
I want to give Data_reg[15:8] to RAM1 and Data_reg[7:0] to RAM0. I use the Schematic design. but I cant separate the Data_reg[15:0] by the wires. How can I do?
 

Have you ever tried to use a bus, and then separete? for example, you will take all the data[15..0] out by the bus, and then, to wire then until your location. Don´t forget to name the bus, for example, data_reg[15..0] and then naming the wires, for example data_reg[4]. good luck!!

Breno
 

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