The routing matrix in high-end FPGAs

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bibo1978

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FPGA routing Matrix

I was wondering if anyone can tell me more information about the routing matrix in the high-end FPGAs especially the two dimension matrices, Also I would get more intact with placement constraints and any success stories regarding this area would be very educating
 

FPGA routing Matrix

If you are using Xilinx ISE, launch FPGA Editor, load a Virtex NCD file, enable all the line/wire buttons, zoom in, and you'll see all the used and unused interconnects.
 

Re: FPGA routing Matrix

Do you mean interconnection Matrix --> Place and route

Horizontal and Vertical interconnect, direct connection and general purpose interconnect..

u can use the XILINX EPIC M1 design to get the details on how chip after design wud look like.

Take a look at this

h**p://www.cedcc.psu.edu/ee497i/xilinx/M1_guide.html

h**p://vlsi1.engr.utk.edu/~jkrumm/project/FinalReport/node6.html

Tutorials: h**p://homepages.wwc.edu/staff/stirra/classes/engr433/hiertut/

With regards,
 

Re: FPGA routing Matrix

thanks ok,

but I need more technical information about the routing delay of the routing matrices I know the routing matrices places, extra but i need info about this
 

FPGA routing Matrix

If you are using Xilinx FPGA Editor, highlight the desired nets and click Tools -> Delay.

If you want to know the delays of unrouted paths, then that's not possible because routing affects delay.

Your question is unclear. Maybe if you tell us more about your project, someone may give you a better answer.
 

Re: FPGA routing Matrix

echo47,

I already know how to see each connection delay.

I will describe a bit my problem, most of my designs are time critical and I pack them usually in the smallest "less cost" FPGA, however due to this tight time constraints I must use RPMs other wise my design will not be optimized and I won't meet this timing requirements, and although RPMs are my only savior but it took me a lot of time and random positioning to meet my time requirements, I am trying to get more details about the routing matrices delay in various aspects to have some clear rules in my RPM designs
 

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