hi
please note to attached file.
1) what is the role of R1 resistor and why this value is selected for it?
2) for opamp, there are restiction as slew rate and gbw(gain band width) and noise. for a special signal career and data ( their frequency and amplitudes),what limits are settle on opamp?
namely for supposed f_carrier and f_data, what must be gbw of opamp?
for supposed amplitude of data signal, what must be slew rate of opamp?
thanks
Circuit makes no sense. You've got an UNDEFINED op amp with no feedback. No way of knowing what the resistor is for without knowing what the op amp is. Running an opamp open loop is never a good thing.
Opamp and comparator sadly share the same symbol. But they are different.
I guess initially the schematic used a comparator, which needs a pullup.
But then some one decided to misuse an Opamp as comparator but missed to remove the pullup (an Opamp needs no pullup)
Circuit makes no sense. You've got an UNDEFINED op amp with no feedback. No way of knowing what the resistor is for without knowing what the op amp is. Running an opamp open loop is never a good thing.
this circuit is used to create zero and one( in digital domain) as zero volt and 5 volt.
in open loop amplifier it goes to saturation( ideally to vcc or vee), so here an open loop amplifier has been used.
2) for opamp, there are restiction as slew rate and gbw(gain band width) and noise. for a special signal career and data ( their frequency and amplitudes),what limits are settle on opamp?
namely for supposed f_carrier and f_data, what must be gbw of opamp?
for supposed amplitude of data signal, what must be slew rate of opamp?
thanks
Basically think of a period you need, eq at highest data rate. Then decide on what
percentage of period you can live with eaten up by OpAmp/Comparator response
time. I am not a designer in this topic but would think 10% of period for settling
(=90% legit usable pulse) makes sense. Then you can can look at how much time
it takes to settle, the rest must be allocated to slew rate. And then do that simple
calculation.
Note receiver side has min specs it needs, so that drives the design of Tx side.
Basically think of a period you need, eq at highest data rate. Then decide on what
percentage of period you can live with eaten up by OpAmp/Comparator response
time. I am not a designer in this topic but would think 10% of period for settling
(=90% legit usable pulse) makes sense. Then you can can look at how much time
it takes to settle, the rest must be allocated to slew rate. And then do that simple
calculation.
Note receiver side has min specs it needs, so that drives the design of Tx side.
hi danadakk
can i ask you what is reference of attached text by you?( i mean 4.8 using opamp as comperator)
thanks
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hi danaddk
thanks for respond
can i ask you what is reference or main text of "4.8 using opamp as comparator"
i am not familiar with open collector comparator circuits. what are they?
thanks again.