The relationship between Vdsat and Vth(sat)

[jamesbond939]

This is a basic question.

From the square-law model:
Vdsat = Vgs - Vth

If Vth of a process increase, we'll need higher Vgs to turn the device on right? In other words the Vdsat will remain the same for different Vth?

Why do we say that when Vth of a process increase, the headroom will decrease?

 

[erikl]

Re: Vdsat and Vth(sat)

Vdsat = Vgs - Vth

What you name "Vdsat" just marks the transition voltage between the linear (or triode) and the saturation region (or the transition from weak to moderate/strong inversion) for any drain current Id, see the dotted curve in this Id vs. Vds plot from Wiki; it has nothing to do with the saturation voltage of an individual MOSFET.

If Vth of a process increase, we'll need higher Vgs to turn the device on right?

Right.

In other words the Vdsat will remain the same for different Vth?

Yes, by your definition. But again: it's not the saturation voltage!

Why do we say that when Vth of a process increase, the headroom will decrease?

Because the difference between the supply voltage and the needed Vgs decreases. The headroom for the control voltage decreases.

 

[ankitgarg0312]

Re: Vdsat and Vth(sat)

we use mosfets in diode configuration a lot of time to generate bias and current sources,,,
these diode are made by connecting drain and gate terminals so vds=vgs and device will be always in saturation forever...

with increase in vth u will increase vgs to maintain overdrive for mosfet ,,,
increase in vgs will increase vds in diode configurations so voltage headroom for other devices (m1) will decrease .... see diagram in attachment

 

[jamesbond939]

Re: Vdsat and Vth(sat)

Thanks for the reply. I have some further questions.

Assume my design does not contains diode connected structures.
Also assume that there's no reduction in supply voltage.

I'm only using simple current mirror and high-swing cascode current mirror. Will the increase in Vth reduces the voltage headroom for my design.

I know that the cascode current mirror might have this problem because it needs 2VDsat+Vth in order for both of the transistor to be in saturation. But in high-swing cascode current mirror, I only need 2VDsat to make sure that the transistors is in saturation.

Does that mean that for current mirror design, we only need to worry about voltage headroom when the Vth increase for cascode structure?

Is there any other structures other than cascode current mirror and diode-connected transistor in analog design that have the problem with voltage headroom when the Vth increase?