The psot-sim of MOM-cap

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mitgrace

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DearAll :

Does any other have good to extract the MOM-cap (cap fringer) , Now I design
0.18um MOM-cap with VIA. I use calibre to do extraction, But I found the command files mo define VIA-to-VIA information, So that the cap is low than the practical ,DOes anyone have good method to expect the value. Thanks
 

then u can use less vias so your extracted cap is close to reality.
 

The calibre-xrc files don't deifne VIA information, If I use the less VIA, Does the cap is different ? I will try it , Thanks.

I have another question , Does you around the Nwell to ring the MOM-cap ,
if we don't use Nwell to around it. Do anyone have any comment . Thanks
 

Anyone could give some information about MOM? The layout is preferred.
Thank you very much!
 

I attach a short application note "MOM capacitor design challenges and solutions" that addresses the questions discussed here.

Regarding vias - if you remove vias, this would decrease capacitance density and probably increase series resistance of MOM capacitor. Don't do this if you want to achieve maximum possible capacitance density.

Max
 
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