the problem of well isolation

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tanghua_0407

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enhancement moscap

hi ,all ,in layout,the C always be isolated with the Psub by nwell. I find that the N well can be connected to vss vdd or no voltage at different occasion ,what is the difference of different connection,thx.
 

problem with well

As the bulk of PMOS transistors, the n-well is usually connected to VDD, or at least to a higher potential than the source(s). If the n-well is the node of a P-MOSCAP, it represents the negative node of the C (poly then positive), hence can be connected to any potential between GND & VDD, also directly to GND (or VSS). I think it should never be left unconnected.
 
what is well isolation

Tan,

The nwell is always to connected to highest potential to reverse bias the p n parasitic diode between n well and psubstrate.....
I have never seen the case of connecting nwell to gnd.... and it is not
preferable to left the nwell floating as it leads to kink (floating body) effect and other second order effect.... floating welll effect is prevalant in SOI technology also..
 
deepak242003 said:
The nwell is always to connected to highest potential ...
Click to expand...
Sorry, deepak, this is not correct; s. my previous post to this thread.
I've often used enhancement MOSCAPs (poly over nwell), e.g. as filter capacitors between VDD & GND. In this case, nwell as the negative terminal is connected to GND, poly to VDD. Such a MOSCAP achieves the highest capacitance per area, and it's a good idea to fill otherwise unused areas with such filter caps.
 
hi erikl,

I assume in MOSCAPs gate is taken as positive terminal(VDD) and diffusion is taken as negative terminal(VSS).....

nwell is again connected to Vdd to reduce any noise if present..

Is there any technical reason to connect nwell to GND in your case......??
 
deepak242003 said:
I assume in MOSCAPs gate is taken as positive terminal(VDD) and diffusion is taken as negative terminal(VSS).....
...
Is there any technical reason to connect nwell to GND in your case......??
Click to expand...
Hi deepak,
if you create a poly over p-substrate enhancement MOSCAP, below the positive poly an n+ enhancement layer is formed, which means another n+/p junction in series to the MOSCAP. Clearly the cap/area value of 2 caps in series is lower than that of a single cap/area, in this case even much lower, because the second cap (n+/p) doesn't make use of the thin gate oxide, but has a much wider junction width (because of the lowly doped substrate).
So the poly over n-well MOSCAP achieves the highest possible cap/area ratio. For a VDD to GND filter cap, the n-well has to be connected to GND. But you can use such a MOSCAP also in a floating arrangement, still the n-well has to be the more negative terminal. The potential difference must be > Vth to generate the enhancement layer.
A further application field - apart from VDD-GND filtering - is for compensation caps, which sometimes need high cap values. Of course it has to be secured, that Vdiff > Vth .
 
hi erikl,

Thanks for your patient and nice explanation... I got most of the issues.. however I m finding difficulty in finding any document related to enhancement MOSCAPs that can make me understand all the issues better... I will appreciate if you can provide any related (especially formation of n+enhancement layer) document..
 

Nwell can be connected to GND if it is used as a deep isolation ring, for expample between analog and digital part. In this case there is nothing in the N-well except n+ active tap connected to GND.
 

deepak242003 said:
I will appreciate if you can provide any related (especially formation of n+enhancement layer) document..
Click to expand...
Hi deepak,
actually this is such basic, that you'll find info about this topic in any good technology or design book about CMOS technology, e.g. in Behzad Razavi "Design of Analog CMOS Integrated Circuits", Chap. 17 CMOS Processing Technology, Sec. 17.7 Device Fabrication pp. 619 ff (Int. Edition 2001). Or just google for enhancement moscap .
Cheers, erikl
 

Floating substrate create huge Noise
 

Hi erikl,
Do u mean that the diffusion are also connected to VSS in a MOSCAP since it will not let the parasatic diode to be forward biased. And the poly can be connected to the +ve voltage wrt the nwell.

Correct me if am wrong.

Regards,
Sandeep
 

sandeep_torgal said:
Hi erikl,
Do u mean that the diffusion are also connected to VSS in a MOSCAP since it will not let the parasatic diode to be forward biased. And the poly can be connected to the +ve voltage wrt the nwell.

Correct me if am wrong.

Regards,
Sandeep
Click to expand...
I think you are right; I just wondered about your expression "diffusion ... also connected to VSS". The nwell is made up of the nwell diffusion, hence cannot be separate(d) from it, i.e. the nwell is identical with the nwell diffusion, and there in no other diffusion (at the location of the enhancement MOSCAP) - apart from the polycide implant, which only affects the poly.

The usual parasitic diode between the nwell & substrate (nwell=cathode), which always is reverse biased, is short-circuited when the negative terminal of the MOSCAP (the nwell) is connected to GND.

Cheers, erikl
 

Hi Erikl,
I have several problem. If you connect Nwl to GND, how can you make sure the nwl/psub diode will not forward biasd even they are shorted to GND(for the leakage current will flow in psub and make voltage drop)
other problem, if Nwl is connect to VDD, and poly to lower voltage , i don't think it will affect the cap/unit, MOSCAP operate in accumulation is as same as in inversion under the gate.
please give me correction. tks.
 

Hi Mestc,
Mestc said:
If you connect Nwl to GND, how can you make sure the nwl/psub diode will not forward biasd even they are shorted to GND(for the leakage current will flow in psub and make voltage drop)
Click to expand...
In this case you create a single contact overlapping both the n-well and the substrate (similar to the common contact of source and substrate of a substrate nfet). By this you ensure deltaV=0 between nwell and substrate. No voltage drop - no forward biasing.

Mestc said:
other problem, if Nwl is connect to VDD, and poly to lower voltage , i don't think it will affect the cap/unit, MOSCAP operate in accumulation is as same as in inversion under the gate.
please give me correction. tks.
Click to expand...
You are right - in principle. However, with poly being negative wrt. the nwell, you create a positive accumulation layer in the nwell, thus producing another pn-junction in series with the accumulation MOSCAP. Moreover, this junction produces a relatively wide depletion layer (because of nwell's low doping), i.e. a low cap/area value, which mainly determines the overall cap/area value of the 2 caps in series. Not just a good idea for a small MOSCAP - and never seen. ;-)

Cheers, erikl
 

Hi,
If u tie your substrate to ground at the point at which u connect the MOSCAP to ground then i don't think there will ever be a problem with forward biasing...
As for the second part of ur post i think the answer lies at Erikl's 3rd post where he says "The potential difference must be > Vth to generate the enhancement layer."

Oups...didn't see the reply...xexe
 



hi erikl,
can i inverter the polarity for the MOSCAP:
can i tie the nwell to vdd, while poly to a lower voltage,
is the same capacitance got?

Jeff
 

jfyan said:
can i invert the polarity for the MOSCAP:
can i tie the nwell to vdd, while poly to a lower voltage,
is the same capacitance got?
Click to expand...
No, Jeff,
s. my. answer in this thread from Fri, 24 Jul 2009 19:09 (following: "You are right - in principle.")
erikl
 

You have to consider the MOS cap as a MOSFET, and if you
want a fairly high capacitance that is also fairly invariant
(a critical thing for distortion) you need to be as far into the
enhancement as you can push it. You most certainly to not want
to be anywhere close to the device threshold as C-V swing is huge
there. Also at light inversion the D/S resistance to the center
of the bottom plate can be increased, killing the Q. An NWell,
N-contacted, depletion mode cap is a more friendly structure.
Which one you have, depends on the foundry. You trade
isolation for (some degree of) reversability.

Now, N-well tied to VDD directly may not be your friend for
supply-noise / coupling reasons. But you would like that
potential. You could consider making a ground-referred
VcapH node using a large filter bank and a resistive feed.

Look at a foundry C-V curve for PMOS (or a depletion
NMOS / NWell structure, whatever is the one you have)
and it will tell you where the capacitance is nvariant, and where
it is not.
 


hi Erik,
thanks for your reply.
but, for poly over nwell cap,i think it is very close to MIS (metal-isolator-semiconduction) cap, and many references said that there is still a same capacitance (~cox) when Vpoly is enough lower than the voltage on nwell (low frequency).
here "enough" means, the generated "hole" is much more than doping level.

Jeff
 

Re: inversion MOSFET against enhancement MOSFET


Sure, you're right, Jeff: a MOSCAP has a larger cap/area ratio than a MIS (or even a MIM) cap: the isolation layer of a MOSCAP (the gate oxide) is considerably thinner than the field oxide (FOX) of a MIS and still thinner than the (possibly high k) isolation layer of a MIM cap.

Your former question, however, was:
jfyan said:
can i invert the polarity for the MOSCAP: can i tie the nwell to vdd, while poly to a lower voltage, is the same capacitance got?
Click to expand...
Here, my answer still is: no. If the poly is negative against the n-well (with a min. difference >≈ Vth), a p+ inversion layer will build up below the poly, creating a reversely polarized junction in the n-well in series with the gate oxide cap. Due to the rather low doping of the n-well, this reversely polarized junction produces a relatively wide depletion width, resulting in a low cap/area ratio of this junction cap. Being in series with the proper gate oxide cap, this low cap/area ratio junction cap reduces the overall cap/area ratio considerably (if not actually determines it).

Hence an inversion layer MOSCAP (n-well positive, poly negative) - due to the serial junction cap - will always show a smaller cap/area ratio than an enhancement (or: accumulation) MOSCAP (n-well negative, poly positive).

Hope I could explain this comprehensibly!?
erikl
 

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