flamingo
Member level 4
The lowest "noise" floor of FFT in Hspice is about -110dB due to my simulation results, and noise floor of output signal is only -65dB. You can refer to the pic below.
what does lead to the high "noise" floor in fft analysis, the circuit noise or simulator error? what about the value of the noise floor that we can accept for a design? and most important thing is how to reduce it to a acceptable level.
My amplifier works as signal conditioning before a 10bit ADC.
**broken link removed**
what does lead to the high "noise" floor in fft analysis, the circuit noise or simulator error? what about the value of the noise floor that we can accept for a design? and most important thing is how to reduce it to a acceptable level.
My amplifier works as signal conditioning before a 10bit ADC.
**broken link removed**
