the mos capacitor in deep submicron process ( 0.35 um)

[xihuwang]

Hi, every one :
I am working on a pll project. The LPF capacitor needed is 50pF. The only
capacitor I can use is mos capacitor.
I have below questions want to ask :
1. If the TOX = 7nm ( 0.35 um process) , how much is the leakage current
for a 50 pF nmos capacitor ( Gate as anode, D S B short to gnd)
2. What is the main cause of current leakage
3. What's the mos capacitor structure should I take to decrease the leakage.
4. Some one tell me , maybe the bird break is the main reason for leakage,
If so , what should I do?

 

[dick_freebird]

Bird's beak is more a problem for D-S leakage. You
are concerned with gate-{D,S,B}, tunneling currents.
The foundry ought to have a spec for max gate leakage
per unit area and per periphery (if that is significant).
Knowing the two you can determine the preferred aspect
ratio.

You might elect to use an I/O transistor for its thicker,
less leaky oxide. At the cost of area efficiency.

You could operate the capacitor at less than full rated
voltage and greatly reduce the gate leakage. However
in this case you would want a low- or 0-threshold (or even
depletion-mode) MOS structure, because effective capacitance
reduces markedly below VT and the channel which you
count on to be a decent ohmic connection to the bottom
"plate", will not be robust near VT.

 

[JoannesPaulus]

In a 0.35um technology, gate leakage is not an issue (7nm TOX is rather thick) but you should check with your foundry!