the mismatch analysis

[chang830]

Hi,
would you share the experience of how you performing the Mismatch analysis in design?

Also, if your PDK did not contains the mismatch model, how do you assess the mismatch charateristics?

Thanks

 

[aomeen]

Hello

In case ypur design kit doesnt support mismatch model, you can run corner analysis. In the model card you will find something called "Section" - From ADE, model files..., you will find three files, one for RF models, one for baseband models and one more file..., in each one you will find in front of each model the current sectione.g for nmos :typical, fast or slow. and for passives: mean, max or min. you can make combination of corners for worst case. for example all nmos are fast with min passives, etc .

If mismatch models are supported, use montecarlo simulation with the instances ending with mis e.g "nmos13_mis", or something like that...

 

[chang830]

Hello

In case ypur design kit doesnt support mismatch model, you can run corner analysis. In the model card you will find something called "Section" - From ADE, model files..., you will find three files, one for RF models, one for baseband models and one more file..., in each one you will find in front of each model the current sectione.g for nmos :typical, fast or slow. and for passives: mean, max or min. you can make combination of corners for worst case. for example all nmos are fast with min passives, etc .

If mismatch models are supported, use montecarlo simulation with the instances ending with mis e.g "nmos13_mis", or something like that...

Hi aomeen,
Thanks for the reply!

But is is not the answer I expected.

In our design, we need to perform the WCS analysis, which just as you described above, i.e, the combinations of all the PVT corners.

But we also need to do the mismatch analysis for mass production. If mismatch model is supported, it is OK for me to perform the MOntecarlo analysis. What I concern is if the mismatch model is not supported, how you do the mismatch analysis?

In my design, I just varies the W,L size of the matched transistors. But we know, the tox, Vth etc,..is also the mismstch source. Then how to handle with it?

Pls. share with your experience.

 

[renwl]

If there is no accurate foundry data, the simulation is useless.

 

[Karthikeya]

Hi,
For finding the mismatch in MOS transistors, Vth mismatch is the major concern as far as I know. This can be found out theoritically by using the relation, sigma=Avt/sqrt(W*L*M) where M is the number of fingers. This is 1σ mismatch...so depending on ur design window u can choose like ±3σ for gaussian distribution. You can observe the mismatch contributed by individual device in simulation by introducing 1σ mismatch in that device.

regards

 

[chang830]

If there is no accurate foundry data, the simulation is useless.

Hi renwl,
it is not correct to think it is useless to do mismatch analysis if without the accurate foundry data.

The mismatch analysis is critical for product yield and even simple mismatch analysis will provide you the information for the mismatch sensitivuty. It would be useful for you to improve the design.

Cheers