Re: Pipeline ADC design
first try to get the Gain, UGB, SR kinda specs from ur basic topology..
for example if u r using 1-true-bit/stage..ur gain error and settling error shd be around 1/4th of 1/2^7..
ur gain error will generate Gain spec of opamp while ur settling error spec will generate ur UGB spec..
now fix ur load cap..now u can get input transistor Gm by CL*UGB..now if ur vdsat is 100mv..u can approximate ur current by 0.5(vdsat*Gm)..
isnt it very simple :spoko: