As far as I remember Verilog, {} are used for composing a single vector from specified parts. So, 1'b0 means heading 0 in a vector, and 2'b00 means two trailing zeros.
hi,
"{}" this is a concatenating operator in verilog.
hear {1'b0, fifo_rddata[15:11], fifo_rddata[7:0], 2'b00} means we are forming a 16 bit register with 1 bit by 1'b0,
5 bits by fifo_rddata[15:11],
8 bits by fifo_rddata[7:0],
and 2 bits by 2'b00.