sun_ray
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Suppose inout is declared in the verilog module of a design. Does it mean that there is an enable in the design such that when the enable is high then inout will be input and when the enable is zero the enable is an output.
Suppose a port is an input to a module written in system Verilog and it needs to be connected to an inout port of another module written in system verilog. Can a variable be declared as logic to connect the inout port to the input port of another module? If the variable declared as logic is not the legal way to connect , please response what is the legal way to connect the input port to the inout port in system verilog.
Suppose a port is an input to a module written in system Verilog and it needs to be connected to an inout port of another module written in system verilog. Can a variable be declared as logic to connect the inout port to the input port of another module? If the variable declared as logic is not the legal way to connect , please response what is the legal way to connect the input port to the inout port in system verilog.