Re: Need ur help !
IMO, C4 & C5 are not intended to add capacitive load to the buffers. If you consider Q1 and Q95 are unity gain buffers, C4 and C5 are just connected across the output of two buffers with the same polarity (ie both terminals of C4 and C5 are moving in the same direction). In small signal analysis, there is no current flow through these two cap and they have no effect in small signal domain.
I guess the purpose of C4 and C5 are trying synchronize the driving signal to Q98 and Q9 in large signal transient because the up and down slew-rate of C4 and C5 are unequal (Consider charging and discharging paths).
For Q93, I guess it is used to provide an additional pull-up path to cutoff the power transistor quickly.