The function of metal layers in VLSI design

[nikhilindia85]

can any body post the material on role played by metal layers in vlsi design?any information regarding different types of metal layers,when we prefer them.i mean their physical significance

 

[jody]

metal layers

the metal is the same, only difference is the layer where he meets.

 

[satyakumar]

Re: metal layers

Hi,
In VLSI design to avoid overlap of metals during routing we use metal layers, there are some rules on using metal layers like which layers are near to silicon and so on.

Thanks and regards
satyakumar

 

[forkschgrad]

Re: metal layers

how serious is the capacitance between metal layers if taken into consideration in vlsi designs?

 

[satyakumar]

Re: metal layers

Hi,
Capacitance is more serious in between metal layers, it increases crosstalk between layers. It also increases delay of the interconnect.

 

[forkschgrad]

Re: metal layers

which is better to use, a wire let say 100um long but 1um wide or a wire 100um long and 5um wide? Given for example we have to connect 2 inverters which are located too far from each other.

Added after 43 seconds:

both are of the same metal layer.

 

[nikhilindia85]

metal layers

can any one tell me how to find out width of the power stripes

 

[vak]

Re: metal layers

which is better to use, a wire let say 100um long but 1um wide or a wire 100um long and 5um wide? Given for example we have to connect 2 inverters which are located too far from each other.

Added after 43 seconds:

both are of the same metal layer.

A wire 100um long and 5um wide is better.

 

[forkschgrad]

Re: metal layers

do u think wider metal produces more capacitance than thinner ones?

 

[satyakumar]

Re: metal layers

Hi,

Wide metal layers will have more capacitance, this you can find from basic equation of capacitance. The wide metal layers decreases the resistance so, we should be carefull in choosing thickness. Randomly we can't come to conclusion. How much thickness we have to use depends on curent density, as well as on how much delay it can tolerate.

Generally long interconects are routed using buffers.

Thanks and regards
satyakumar

 

[bg21359]

Re: metal layers

if you use something like 11 layers of metal, usually the top level metal is aluminum not copper for reliability purpose in order to connect to solder bump(C4).
And if you design high performance dense chip, the capacitance between wires at same metal level is far larger than the one between different metal level.
And the metal thickness is not something you can control, you got what foundry provided, which basically define your resistance per box.
You need to think about performance, power, electromigration and routing area together.