the FPGA's GCLK signal don't use as normal IO?

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ZFDok

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gclk spartan 3

ERRORack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "CpuData" (Pad Signal = CpuData)
BUF symbol "CpuData_ibuf" (Output Signal = rsda)
Each of the following constraints specifies an illegal physical site for a
component of type IOB:
Symbol "CpuData" (LOC=P88)
Please correct the constraints accordingly.

i use the xc2s15, the pin 88 is GCLK in put ,but 2i want use it as a normal I signal,
but the design is not compile passed ,who can help me check the error?
 

xst user io on gclk pin

I don't have Spartan-2 stuff installed to try your project, but if you want to use CpuData as an ordinary input, then your UCF file probably shouldn't say "BUFG = CLK".
 

xilinx gclk cpld io

in xc2s15 pin P88 can be used as GCk or any other signal input.
it cannot be used as an output ot I/O pin.
check the data sheet
**broken link removed**

from ur ucf file i see the CpuData signal is contraint as global clock which is wrong
change following line in ucf
NET "CpuData" LOC = "P88" | BUFG = CLK ;
to
NET "CpuData" LOC = "P88" ;
 

gclk or gck type pin

yes, i used "NET CpuData LOC = P88;" in my *.ucf file , it does not compile passed to , it appear the error:
ERRORack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "CpuData" (Pad Signal = CpuData)
BUF symbol "CpuData_ibuf" (Output Signal = rsda)
Each of the following constraints specifies an illegal physical site for a
component of type IOB:
Symbol "CpuData" (LOC=P88)
Please correct the constraints accordingly.
echo47: are you use the ISE compile passed?
 

io is gclk or gck

I believe you can only connect a BUFG to the GCK inputs on the Spartan 2. The IBUF, whether it's created by you or XST is mapped to an IOB which doesn't exist on the clock pins of the Spartan 2.
 

errorack:1107,spartan 2

ZFDok, I can't compile your project because I didn't install Spartan-2 with my ISE. The installer won't run anymore because I've updated ISE with a service pack. Sorry!

tkbits, that's a good point. Page 3 of the Spartan-2 product spec DS001-1.pdf says this: The four global clock pins are usable as additional user I/Os when not used as a global clock pin. But I guess that's true only if you apply this workaround:
**broken link removed**

ZFDok, try it!

The Xilinx documentation has quite a few unclear/confusing issues like that.
 

fpga gclk

The synthesizer detected a signal used as a clock source, so it synthesize it as a bufclk.
once you go to the implementation, ISE finds that a bufclk cannot be put on that pin.

just instruct the synthesizer (in your source code) not to use a bufclk for that signal.
This can be done using the ATTRIBUTE BUFFER_TYPE , specifying IBUFG instead of BUFCLK.
bye
Alba800
 

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