alexan_e
Administrator
The "Flancter" set/clear status flag in different clock domains (application note)
I was searching for a while how to write to a signal from two different processes,
this application note has a very interesting solution that has helped me in my projects.
It can also be used to set a status flag in the rising edge and clear on the falling edge.
Includes both VHDL and Verilog example code
"How to set a status flag in one clock domain, clear it in another, and never, ever have to use an asynchronous clear for anything but reset"
https://www.floobydust.com/flancter/Flancter_App_Note.pdf
Alex
I was searching for a while how to write to a signal from two different processes,
this application note has a very interesting solution that has helped me in my projects.
It can also be used to set a status flag in the rising edge and clear on the falling edge.
Includes both VHDL and Verilog example code
"How to set a status flag in one clock domain, clear it in another, and never, ever have to use an asynchronous clear for anything but reset"
https://www.floobydust.com/flancter/Flancter_App_Note.pdf
Alex