The extraction problem of BJT transistor

[Question]

My design environment is TSMC 0.18UM MM/RF 1P6M SALICIDE 1.8V/3.3V PROCESS PDK (for Cadence) Revision 1.1a. There are some BJT transistors in the circuit. The cell name of BJT is ' vpnp3 ', the view name is ' spectre ' in my schematic. There is no layout pcell of BJT transistor in the PDK, so I make the layout design by myself.

When I run a extraction by the diva rule in the PDK, it will give me a warning massage ' Cannot match terminal counts for vpnp3 ivpcell tsmc18rf '. Because of this problem, I can not clean the LVS. If I use Hercules to run a extraction job, I can get the right BJT transistors. The runset file of Hercules is ' LVS_Hercules_0.18um_MM_1p6m.20a '.

How can I get the right extracted view by diva rule? If I can not get the extracted symbol, how to simulate the circuit?

Thank you.

 

[Fom]

For BJT devices each model correspond to fixed layout. Pcell cannot be used for layout development. Usually TSMC provide GDS file for each BJT model.

 

[selvaraja]

for BJT devices in tsmc CMOS process , foundry do provide fixed layout we can`t draw it on your own .you have to require the gds file from the foundry.