The explanation of clock gating

[sachinmaheshwari]

can anyone explain me what is clock gating?

 

[avimit]

Re: clock gating?

Not all registers in a design are updated every clock cycle. Not every block of a design receives new data every clock cycle. So the clock going into such registers/blocks just drain power for no good reason. To save power, therefore the clocks are stopped on temp basis. This is done using someghing called 'clock gate' which logically** is just the clock anded with 'enable' signal. This process of gating or stopping the clock is called 'clock gating'

**logically its just and operation, practically is a specialized structure to stop the clock without glitches.
Hope it helps
Kr,
Avi
http://www.vlsiip.com

 

[sachinmaheshwari]

Re: clock gating?

thanx for the answer...
but can u tell me in more simple way.?
i understood but still their seem to be some prob.?

 

[A.Anand Srinivasan]

Re: clock gating?

what problem do you have with that reply.... i find everything crystal clear.... pls specify what is your problem with that reply.....

 

[sachinmaheshwari]

Re: clock gating?

i means in simple language can u explain me?

 

[A.Anand Srinivasan]

Re: clock gating?

in simple language it is just the allowing or blocking of clock to certain components of a circuit....

 

[khaila]

Re: clock gating?

i means in simple language can u explain me?

let me try:
Think about Shut-Down or Standby.
The concept of using that modes is to reduce the power consumption of a system.
Each design contains several block.
It may that all the blocks are activated at a time. but later some of them are not activated because they have no task to do; so there is no need to keep them in active mode because it will consume power for free.

One technique that used to implement "Stand-by" mode is to de-assert the clock that feeds the blocks which the system defines later during its operation that this blocks maybe in inactive mode.
The concept is: While the clock is SWINGing then it will consume power.

The way that we can de-assert clock is by feeding that blocks with PERMANENT level instead of the clock. It is called Gated-Clock.

The name behind Gated-Clock is: Try thinking about AND'gate with two inputs while one input is connected to CLOCK and the other input is connected to ENABLE signal. The output of the AND'gate will feed each block in the design.
So when Enable goes high then the block will be feeded by the system clock else to feeded by permanent level which is LOW.

Actually, Gated-Clock is not implemented as I described upon because it will produces partial clock periods and unwanted glitches at the output of the AND'gate.
There many techniques used to generate Gated-Clock.

 

[tayyeb1]

Re: clock gating?

Gating the clock is same in its excent.But it is often deleterious to gate anything like clock.A practical sequencial circuit runs on one clock.If you do anything with clock of a single flip-flop there would be a propagation delay that is capable to destroy the sequence.

 

[crinud]

Re: clock gating?

hai,


simply way of understanding the clock gating is data should control the clock.ie.....
if u take a normal flip-flop with enable (e) pin.the whole flip flop is controlled by the by this enable pin.this is called clock gating.this type of technique is used to save the power.because clock is the only pin which will use lot of power in the designs .if u use clock gating technique there is also change of getting glitch at the output.

 

[tkbits]

Re: clock gating?

Clock gating is simply enabling/disabling the clock signal with a simple gate. You must be strict with your timing, otherwise the act of enabling the clock signal will cause immediate (and therefore an extra) clock event. The gating signal must also be glitch free, if you want to avoid extra clock events, or worse, metastability.

 

[ubna]

Re: clock gating?

Clock gating is simply putting an AND gate whose inputs are the clock signal and the gating control signal. the output will be given to the register or flop...