The event drive in Verilog?

[AlexWan]

In the Verilog 1394 standard, it support the event-base.

Can anyone tell me the detail information about the event-base in simulation?
Or give me some source, links?

Thanks

 

[eda_wiz]

c the attached ppt

**broken link removed**

Event vs. Cycle Based:
An event driven simulator typically tends to be faithful to the semantics set forth by the HDL. Essentially, at every time unit, the "kernel" de-queues any events that are due at that time unit which in turn trigger actions for the "execution" unit which in turn may schedule new events with the "kernel". This cycle continues until there is nothing more to do at the current time -- in practice, it is not unusual to see hundreds of such iterations at a given simulation time. The kernel then advances time to the next simulation time (or to the next earliest scheduled event). Typical event driven simulators also place little or no restriction on what language constructs are legal making them very versatile.

The other variety is "Cycle Based" which analyzes the HDL design and partitions the design into synchronous and asynchronous tasks. A majority of the hardware described within the HDL design tends to be synchronous to just a few signals (for example clocks, enables, etc.). The idea behind cycle-based-simulation is to reduce the number of iterations a typical event-driven-simulator goes through to arrive at the final values at the outputs. This is achieved by evaluating all tasks only on the event boundaries. For example the entire circuit that is dependent on a given clock domain only needs to be executed (in the proper order) once for most designs. Done properly, this can result in huge performance gains (in the order of 10 to 100x). However, this is not without its flaws. A typical cycle-based-simulator places a very large set of restrictions on the coding style and restricts the set of language constructs that are legal for it (but, this is also true of HDL synthesis tools). A second disadvantage is that you cannot perform timing simulation without resorting to an event-driven simulator, or using a static timing analysis tool in conjunction with a cycle-based-simulator. Even though, a cycle-based-simulator strives to achieve the same effective results as an event-driven simulator, sometimes this is not the case. So, most people who use cycle-based-simulators, also end up using an event-driven simulation to ensure that the results are the same. Cycle-based simulation is a boon for very very large simulations which could easily take months to simulate using even the fastest event driven simulator.