Hello, joe2moon
Yes, You are correct.
It's my mistake.
When I made progess project that crypto-module, I used both language (VerilogHDL, VHDL)
I did concurrently both language. so, I confused.
For test, I used Altera Excalibure. At time, I had used PE and SE modelsim.
There are "Full-bus function simulation" that Excalibure verification name.
Full-bus function simualtion some alike HW checking simulation with PLI, FLI. (Before I was only using PLI at Verilog-XL)
SE can run PLI and FLI, but PE can't run FLI.
sorry my wrong.