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The Cadence SOC Encounter is targeted for RTL to GDSII flow where you start your design with HDLs/SystemC and synthesize to generate/simulate gate level netlist, do auto place & route, to DFM and generate GDSII. This flow always has presence of standard cells to enable all the stuff.
The virtuoso on other hand is targeted for custom design (mainly Analog/RF design) which uses spice, s-param based models for simulation. Because of complexities of Analog, this flow is not as automated as Encounter.
IC compiler is a place & route tool from Synopsis, which works in conjunction with design compiler (DC for synthesis).
SOC Encounter is a platform from Cadence for RTL to GSDII flow which uses RTL compiler (RC for synthesis).
Ultimately both are doing same thing by different EDA vendors.
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