Aug 17, 2007 #1 A ameed Advanced Member level 4 Joined Jun 28, 2007 Messages 106 Helped 6 Reputation 12 Reaction score 1 Trophy points 1,298 Location INDIA Activity points 1,931 hi all, For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit to increase the yield. But finally in a big chip design the designer has to be dependent on the EDA tools to do this. Most of the EDA companies have come out with tools which take care of these DFM issues. But the universal success of such tools is still unknown!! can anyone suggest:?:
hi all, For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit to increase the yield. But finally in a big chip design the designer has to be dependent on the EDA tools to do this. Most of the EDA companies have come out with tools which take care of these DFM issues. But the universal success of such tools is still unknown!! can anyone suggest:?:
Aug 17, 2007 #2 A analog_prodigy Full Member level 2 Joined Jul 19, 2007 Messages 140 Helped 14 Reputation 28 Reaction score 2 Trophy points 1,298 Location India Activity points 1,936 asic design I think, synopsys tools are good for digital and cadence tools are good for analog chips. Monte Carlo analysis helps us in determining the yeild.
asic design I think, synopsys tools are good for digital and cadence tools are good for analog chips. Monte Carlo analysis helps us in determining the yeild.