the configuration space logic

hello friends,

can someone help me to take me out of confusion

i want to build an application going to interface to pci bus (there is no os)

i am refering the book "pci system architecture" by tom shanley

in book chapter 19: configuration register (pg 384) gives how to use base address register

i am little bit of confuse there

say for memory example: assume that FFFFFFFFh is written to BAR (who is going to write that and why?) at dward 04d and value read back is FFF00000h (who is going to rede?)

programmer then writes 32 bit base address into register ???

now i am not getting

if i am going to use 9054 ic which is with eeprom as per my understanding on power on eeprom is going to load into the configuration space of 9054 (how i didn't get) where i will tell what are my application space requirements (write?)

then master will read the configuration space and BAR and assign the memory

then why programmer has to write base address into BAR

priya