samayanaya
Newbie level 4
- Joined
- Jun 22, 2010
- Messages
- 7
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Location
- South Africa
- Activity points
- 1,339
I did a design using the DLP3000 with its controller. I based my design on the evaluation board just with less sdram (128MB instead of 256MB) and no FPGA. The functionality of the FPGA was to provide video data to the DLP controller. So put a video decoder down with BT656 digital output. The board functionality is controlled by a AVR32 cpu.
Everything functions but I get a vertical scrambled picture on the dlp3000. Its random vertical lines. Horizontal has nothing. I have checked the clocks are correct, I have the correct startup sequence and power supplies are stable. I really need some advice on what else to check. Our very bright mechanical engineer damaged our eval board so I have no reference to check against. TI has also been of VERY little help :bang:
Any suggestions would be welcome - Thanks
Everything functions but I get a vertical scrambled picture on the dlp3000. Its random vertical lines. Horizontal has nothing. I have checked the clocks are correct, I have the correct startup sequence and power supplies are stable. I really need some advice on what else to check. Our very bright mechanical engineer damaged our eval board so I have no reference to check against. TI has also been of VERY little help :bang:
Any suggestions would be welcome - Thanks
