windwarrior
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i generated functional patterns(.evcd files) through gate-level simulation(vcs), and then fed the patterns into tetramax for fault simulation.
but a lot of errors occurred during tetramax logic simulation(fault-free simulation), just as follows:
741 memaddr_comb[0](exp=0, got=x)
what should i do to fix this problem?
but a lot of errors occurred during tetramax logic simulation(fault-free simulation), just as follows:
741 memaddr_comb[0](exp=0, got=x)
what should i do to fix this problem?