magnonistefano
Newbie level 4
Hello,
I am a Tetramax Newby and i am trying to use load functional test vector generated by modelsim.
I generate the modelsim test vector following this procedure:
and i load such a VCD in tetramax
set patterns external ./externalFaults/alwcpuSimDump.vcd -insensitive -strobe rising clock -strobe offset 180 ns
First error apperaing was the fact that signals where capital and lower case in different files (solved by using -insensitive).
Second problem is that std_logic_vector are not recognised while parcing the VCD.
i get an error like: missing definition (No such port "adr_o[15]"). (V4-1)
but in the VCD the port is present as shown here:
as well as it is present in the netlist as shown here:
did anyone experienced such a problem?
Any idea about why this happens or how to fix it??
Cheers,
I am a Tetramax Newby and i am trying to use load functional test vector generated by modelsim.
I generate the modelsim test vector following this procedure:
Code:
vsim work.TbTop
view wave
wave create -pattern none -portmode out -language vhdl -range 15 0 //tbtop/outport
restart TbTop.vhd
vcd dumpports -file alwcpuSimDump.vcd /TbTop/alwcpu66/*
run 1000
quit -simand i load such a VCD in tetramax
set patterns external ./externalFaults/alwcpuSimDump.vcd -insensitive -strobe rising clock -strobe offset 180 ns
First error apperaing was the fact that signals where capital and lower case in different files (solved by using -insensitive).
Second problem is that std_logic_vector are not recognised while parcing the VCD.
i get an error like: missing definition (No such port "adr_o[15]"). (V4-1)
but in the VCD the port is present as shown here:
Code:
$var port 1 <0 clk_i $end
$var port 1 <1 rst_i $end
$var port 1 <2 cyc_o $end
$var port 1 <3 stb_o $end
$var port 1 <4 sel_o $end
$var port 1 <5 we_o $end
$var port 1 <6 ack_i $end
$var port [15:0] <7 adr_o $end
$var port [15:0] <8 dat_o $end
$var port [15:0] <9 dat_i $endas well as it is present in the netlist as shown here:
Code:
entity cpu is
port( CLK_I, RST_I : in std_logic; CYC_O, STB_O, SEL_O, WE_O : out
std_logic; ACK_I : in std_logic; ADR_O, DAT_O : out std_logic_vector
(15 downto 0); DAT_I : in std_logic_vector (15 downto 0));
end cpu;did anyone experienced such a problem?
Any idea about why this happens or how to fix it??
Cheers,