Tetramax. error in parcing extended VCD

[magnonistefano]

Hello,

I am a Tetramax Newby and i am trying to use load functional test vector generated by modelsim.

I generate the modelsim test vector following this procedure:

vsim work.TbTop
view wave
wave create -pattern none -portmode out -language vhdl -range 15 0 //tbtop/outport
restart TbTop.vhd
vcd dumpports -file alwcpuSimDump.vcd /TbTop/alwcpu66/*
run 1000
quit -sim

and i load such a VCD in tetramax

set patterns external ./externalFaults/alwcpuSimDump.vcd -insensitive -strobe rising clock -strobe offset 180 ns

First error apperaing was the fact that signals where capital and lower case in different files (solved by using -insensitive).
Second problem is that std_logic_vector are not recognised while parcing the VCD.

i get an error like: missing definition (No such port "adr_o[15]"). (V4-1)
but in the VCD the port is present as shown here:

$var port 1 <0 clk_i $end
$var port 1 <1 rst_i $end
$var port 1 <2 cyc_o $end
$var port 1 <3 stb_o $end
$var port 1 <4 sel_o $end
$var port 1 <5 we_o $end
$var port 1 <6 ack_i $end
$var port [15:0] <7 adr_o $end
$var port [15:0] <8 dat_o $end
$var port [15:0] <9 dat_i $end

as well as it is present in the netlist as shown here:

entity cpu is
   port( CLK_I, RST_I : in std_logic;  CYC_O, STB_O, SEL_O, WE_O : out 
         std_logic;  ACK_I : in std_logic;  ADR_O, DAT_O : out std_logic_vector
         (15 downto 0);  DAT_I : in std_logic_vector (15 downto 0));
end cpu;

did anyone experienced such a problem?
Any idea about why this happens or how to fix it??

Cheers,

 

[vishalmistry]

first thing I noted that you have generated a .vcd file and not a .evcd file. Both are different in some extent. you can generate a standard evcd file using

$dumpports(top_module_name,"test.evcd",,2);

top_module_name is the module from where you want to dump the ports.
test.evcd is the name of evcd that will be generated
2 is the industry standard for evcd format.

Try this option. Add this command in testbench file.

you can generate evcd from command line as well. This is the command line for ncsim and for modelsim it may vary. please see document for modelsim.

database evcddb -evcd -default -into test.evcd
probe -create top_module -evcd -evcdformat 2 -all -depth all


Hope it will work.

 

[Miten Chotaliya]

Hi All,

I am trying to read evcd in tetramax using below command.

set_patterns -external *.evcd -strobe_period { 100 ns } -strobe_offset { 95 ns }

but is showing error like.

Error: Line 28 (*.evcd), missing definition (No such port "port_name"). (V4-1)

End reading 0 patterns, CPU_time = 0.00 sec, Memory = 0MB

Actually port_name is there inside evcd file & netlist.
Could you please help to read patterns..?

Thanks,
Miten

 

[maulin sheth]

Hello All,
Can I know your purpose of loading vcd or evcd in TMAX?

Thanks & Regards,
Maulin Sheth

 

[Miten Chotaliya]

Hello All,
Can I know your purpose of loading vcd or evcd in TMAX?

Thanks & Regards,
Maulin Sheth

Hi Maulin,

How are you..?
Well,
I need to read evcd patterns in tetramax to do fault simulation on that patterns.
I have no source regarding evcd patterns.(like, I did not generate evcds,no info of netlist & libs).I cross check on uper level that every thing is fine regarding netlist & libs and that port is also there in netlist.. I want to know why I am getting this error.Eventhogh my syntax are also same as TMAX.

Thanks & Regards,
Miten Chotaliya

 

[maulin sheth]

This types of problem happens when generated evcd format does not meet the evcd IEEE 1364 standard. For that you just need to check the PLI you used during simulation/ during evcd generation.

If evcd does not meet the standard, thn TMAX not able to read evcd format properly.
Can you please put the line where this error came?

Thanks & Regards,
Maulin Sheth