Tetramax ATPG untestable reasons...

[magnonistefano]

Hello.

I am new to tetramax so I apology if I'm saying some no sense.
I am trying to generate some test patterns for alwcpu, a small open source cpu but I am finding some problems.

It looks like even though Tetramax detects 14252 possible faults it does not manage to create test patterns for not even one. Any Idea about why could I have this problem? I really have no idea!

here I post what the shell return

add faults -all
14252 faults were added to fault list.

run atpg
ATPG performed for stuck fault model using internal pattern source.
----------------------------------------------------------
#patterns #faults #ATPG faults test process
stored detect/active red/au/abort coverage CPU time
--------- ------------- ------------ -------- --------
Begin deterministic ATPG: #uncollapsed_faults=109, abort_limit=10...
0 0 0 0/72/0 0.00% -0.00

Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 0
Possibly detected PT 0
Undetectable UD 126
undetectable-tied UT (94)
undetectable-blocked UB (32)
ATPG untestable AU 14126
atpg_untestable-not_detected AN (14126)
Not detected ND 0
-----------------------------------------------
total faults 14252
test coverage 0.00%
-----------------------------------------------
Pattern Summary Report
-----------------------------------------------
#internal patterns 0
-----------------------------------------------


It looks like everything is UNTESTABLE.... but i do not know why...
tnx for the help,
Best,
Stefano

 

[xworld2008]

have you synthesis rtl and insertion scan chain?

 

[michealwolf]

DRC check result?

 

[magnonistefano]

hi.

I am actually trying now just with the controll unit. without scan chain i can cover 17% of the stuck at fault

I am now trying to insert the Scan chain but i am getting some errors.

what i simply did is adding:

sc_in : in std_logic;
sc_en : in std_logic;
sc_out : in std_logic;

i generate the netlist using the design compiler and i tried to use them in my Tetramax script as follow:
# Add scan_in and scan_out port information
add scan chain myscan sc_in sc_out

#Activate scan enable signal
add scan enables 1 sc_en


but when i launch the script i get the following error:
Begin scan chain operation checking...
Error: Chain myscan blocked at PO gate sc_out (117) after tracing 0 cells. (S1-1)
Error: Design rules checking failed: cannot exit DRC command mode. (M100)
------------------------------------------------------------------------------------------------------------------------------------

i did not modify the compiling script. i saw that many tutorial for DFT use the commands:
set_scan_signal...............
check_test
insert_scan

but i do not have those command in my Synopsys installation even if i have DFT installed.

do i have to include somethink in The compilation script?

Tnx,
Stefano

 

[sunilbudumuru]

Hello Friend,

It looks you haven't followed the correct flow.

1. Synthesize (design compiler in ur case)
2. Insert test structure using test logic insertion tool (may be DFT Comlier in ur case)
3. Look for violations during post "dft_drc" (dft_drc after insert_dft).
4. Analyze and Fix the DFT-DRC violations like the one u got above.
5. Once your test logic insertion is done without any issues in test logic insertion tool then use TetraMax tool
6. Use the valid fiels (like SPF from DFT-C, netlist) to generate the test patterns..

Finally, U'll see the final test coverage and the number of faults detected etc..
I put it as simple as possible for your understand. Need efforts from ur side to see final results ..

Good luck

Sunil Budumuru

 

[magnonistefano]

tnx a lot.

the problem was that my system had no scan chain so i had to firts create a scan chain with DFT compiler and than i could use it from tetramax and get a high fault coverage.

Now, i do not know weather i can ask another question in the same thread or not, however my problem is that i DO NOT want to use scan chain.

I am trying to model throughout tetramax some software testing for a processor. I would like to create a memory where some software is present connected to the processor. let the processor run the piece of code in there and measure the fault coverage achieved with that piece of code. The problem that i have to consider that the piece of code is execute in program order, they are not simply some indipendents test patterns.

Do anyone know if i can do something like that through Tetramax???

tnx a lot again for the help you are giving me!

Best,
Stefano

 

[kornukhin]

Without creating scan chains you can't observe result of stuck-at faults at the primary outputs with high fault coverage.
You can model software tests in simulator (VCS, IUS, Modelsim...) and get coverage reports (block, expression, toggle...). But it still will not be the same as stuck-at faults.