Can anybody explain how to test OTP memories on ATE?
Since it is one time programmable, we can not simply program and read it like RAM. How can we verify that, the OTP memory that has been fabricated is good to go?
Don't have experience on this, so can only speculate...
You might know what data has been programmed in the OTP during fab.
So can you not instruct your ATPG tool to generate test patterns that will perform only read operation from the OTP and later match it off-chip with the programmed data?
ummm...difficult! Let some test-expert answer this.
In any case while using the DUT on ATE you can only read such memory as it is. Generally during fab. such memories have a particular value, all 1s or 0s or something else, which may be read out.
Extra spare memory cells are included in the design of the memory. These rows and columns of cells are accessible only by the testing programs in a special test mode at the factory for cross talk and access time.
Then blank idle current and contents may be tested by the user.
Designs proposed to inject a dynamic charge and sense the charge in an addressed cell have been patented for consideration in industry.
Extra spare memory cells are included in the design of the memory. These rows and columns of cells are accessible only by the testing programs in a special test mode at the factory for cross talk and access time.
Then blank idle current and contents may be tested by the user.