Testbench: variable clock

[dd2001]

How to write a variable clock generator?

always #cycle clk = ~clk;


want to cycle auto increse 10 every #500.


Any one guru can help?

 

[sandusty]

Use several clock sources, then mux those clocks together and that mux controled by counter(s). Since its not synthesisable, you need NOT to worry about the glitchs, load....

 

[karlheinz]

Is this what you want ?


`define cycle_main 100
`define cycle_inc 500
`define inc 10

integer tinc;

initial begin
tinc = 0;
clk <= 0;
end


always begin
#(`cycle_main + tinc)
clk <= ~clk;
end

always begin
#(`cycle_inc)
tinc = tinc + `inc;
end

 

[dd2001]

Well, karlheinz:


It is very close, I just want it functions like a VCO, if feedback 7-bit data changed, then frequency also follow.


Thnaks.