testbench simulation using modelsim.

Hi,
I am trying to simulate a program using testbench on modelsim, but every time it gives me this error on modelsim:

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1
# ** Error: Illegal lpm_address_control property value for LPM_RAM_ROM!
# Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1
# ** Error: Illegal lpm_outdata property value for LPM_RAM_ROM!
# Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1
# ** Error: Unknown INTENDED_DEVICE_FAMILY UNUSED
# Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1
# ** Error: Illegal lpm_address_control property value for LPM_RAM_ROM!
# Time: 0 ps Iteration: 1 Instance: /testhw7/u1/u3/rom1
# ** Error: Illegal lpm_outdata property value for LPM_RAM_ROM!
# Time: 0 ps Iteration: 1 Instance: /testhw7/u1/u3/rom1
# ** Note: simulation done
# Time: 20 us Iteration: 0 Instance: /testhw7

the testbench:
library ieee;
use ieee.std_logic_1164.all;

entity testhw7 is
end testhw7;

architecture structure of testhw7 is

constant clockperiod : time:=40ns;
constant Numofcycles : integer:= 1000;

component hw7
port(clk : in std_logic;
PixelClk : out std_logic;
VGABlankn : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
R : out std_logic;
G : out std_logic;
B : out std_logic);
end component;

signal clk : std_logic;
signal PixelClk : std_logic:='0';
signal VGABlankn : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal R : std_logic;
signal G : std_logic;
signal B : std_logic;


begin
u1: hw7 port map (clk=>clk, PixelClk=>PixelClk, VGABlankn=>VGABlankn,
hsync=>hsync, vsync=>vsync, R=>R, G=>G, B=>B);

clockgen : process
variable cycle : integer range 0 to 1000:=0;
begin
for cycle in 1 to Numofcycles loop
clk<='1';
wait for clockperiod/2;
clk<='0';
wait for clockperiod/2;
end loop;
report " simulation done";
wait;
end process;
end structure;




any help is appreciated.

Dunno..

Googling on "Error: Illegal lpm_address_control property value for LPM_RAM_ROM" found this:

https://alice.physi.uni-heidelberg.de/svn/trd/MCM_WTST_FPGA_designs/trunk/SRC_ALTERA/220model.vhd

So barring more useful replies by others you could read the VHDL code, and see on what conditions it throws that error. Or maybe read some documentation by Altera on that LPM synthesizable model...

Thanks alot, now i got rid of the errors, but the problem it gives me "U" in the output!!!!

U indicates Uninitialized in VHDL. The outputs may not be driven properly

herwis said:

Thanks alot, now i got rid of the errors, but the problem it gives me "U" in the output!!!!

Click to expand...

Glad you found it.

As shanmugaveld pointed out, the "U" are Uninitialized. Depending on your design, an U can be appropriate ... or not. The U during simulation merely means that at that point in time it 1) has not been assigned an initial value at the start, and 2) up until now no assignment with a known value has been made yet.

You can provide an initial value for the registers related with your U signal.