Lets tackle these one at a time.
1. Repeat. It is exactly as you expect. repeat (2) means repeat the following statement 2 times. In your case,
repeat(2) @(posedge clock);
means wait for 2 clocks
2. Using #2 means you are waiting for a fixed period of time. The problem is you are not synchronised to the clock, so you are now likely setting the data/sel/reset just before a clock edge, and probably not quite behaving as you expect. I recommend sticking with the first form, waiting for explicit clock edges.
3. If its not working, then something needs to be fixed. You will need to study the waveform and explore the reason for the errors. Welcome to world of hdl debugging!