testbench for gate level simulation

Hi ,
i want to verify a DUT(total combinational logic) ,so i wrote a testcase like this


`timescale 1ps/1ps
......
......
initial
begin
input1 <= 3'b000 ;
input2 <= 3'b001 ;
input3 <= 3'b010 ;

#2
out_scoreboard = out_from_rtl ;
if(out_scoreboard != expected_output)
begin
$display("Testcase1 : fail");
$finish ;
end


At functional level , i think it is ok , but if i use the same testcase at gate level simulation , is this testcase works ?
because i don't know the exact delays ..
so i cannot expect the output after 2ps , output may come after 3ps ....
so , my doubt is , am i wrote the testcase in a correct way ?
is using the hash(#) delays in testbench/testcase is right ?


my intention is to write a testcase , that suits for functional verification and also for gate level verification .....
so how should i write a testcase ? to use at functional verification and at gate level verification without any modification
please say ..
Thanks in advance.

why you don't used the same testbench as you have used for the RTL simulations?
It is what we did with success, I mean the test bench has i2c/spi eeproms, and the simulation passed for RTL and gated with the same testbench, because the DUT as the same pinouts.

Only in the case, you have a model of AD converter, the sample&hold will capture at a different time the analog signal (real type) and then the simulaiton could not be bit true.

Hi RCA,
Would you explain in detail , please .
Thanks in advance.