Testbench file in VHDL. Help required

[Vijay Vinay]

Hello,
I am new to writing the testbench files in VHDl but I have somehow written a test bench file. The context of the file is as follows

---

Code ActionScript - [expand]
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wait for 100 ns;    
        reset_n_i <= '0';
        wait for clk_128m_i_period*10;
            reset_n_i <= '1';
        wait for clk_128m_i_period;
        fmcw_trig_i <= '1';
        fstep_i <= "1111111100";
        fmcw_bw_i <= "000000000010011100010000";
            wait for 1 ms;
        reset_n_i <= '0';
                assert reset_n_i='0' report "Output is zero, make reset value to 1" severity  Error;
        
                assert fmcw_trig_i='0' report " FMCW modulation works only if fmcw_trig_i=1" severity Error;
        report "End of the simulation";

---

.


What I actually need is that , when I change reset_n_i i =0 ,then it should stop the simulation and should print the above message as "Output is zero, make the reset_n_i value to 1". The same for enable_i also. But it is not working in this manner. Help is appreciated

 

[K-J]

Inside of a process, signals only get updated when the process suspends. This could be because the process completes or because you run across some form of 'wait' statement. In the area where you're not getting the expected result, you've assigned a value to reset_n_i and then immediately check without any wait to see if that value is there. It's not. Reset_n_i is scheduled to be updated...at the next suspend point. The fix is shown below.

reset_n_i <= '0';
[COLOR="#FF0000"]wait for 0 ns;  -- KJ Added[/COLOR]
assert reset_n_i='0' report "Output is zero, make reset value to 1" severity  Error;

Kevin Jennings

 

[Vijay Vinay]

Hello,
I have another doubt. If I make my reset signal to 0 accidently, I should get a message that "The simulation will be ended, Make reset to 1" and the simulation should stop. Once I change the value of reset to 1, the simulation should again start. The same should be applicable for both enable as well as fmcw_trig, in my case. I have written the testbench code in this manner, but I am not getting the desired output. The code is as follows...

wait until reset_n_i='0';
		
		assert (reset_n_i='1') report "The value of the output is fmcw_mod_o when the simulation is ended,    Make reset to 1" severity  Error;
		assert false report"Simulation is ended" severity Error;
		
		wait until enable_i='0';
		
		assert (enable_i ='1' and fmcw_trig_i='1') report " FMCW Modulation will start only when enable_i and fmcw_trig_i=1" severity Error;
		
		assert false report"Simulation is ended" severity Error;

		end process;

.

On running this testbench, when I change reset=0, then I get the message "The value of the output is fmcw_mod_o when the simulation is ended" and the simulation stops. When I try to run the simulation once again by changing the reset to 1, the simulation is stopped and not running further. Whereas if I change the same for enable and fmcw_trig_i=0, the simulation is still running , and the error message is not being displayed and the simulation is not stopped. I don't know how to solve this problem. Help is appreciated.

 

[Vijay Vinay]

Hello,
I need to give the inputs via the testbench which needs to increment after every 10ms. How shall I do this?? Help is appreciated.

 

[ads-ee]

Hello,
I need to give the inputs via the testbench which needs to increment after every 10ms. How shall I do this?? Help is appreciated.

How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment).

 

[TrickyDicky]

How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment).

Instead of giving the simulator lots of work to do with a system clock counter, why not just do this:

---

Code VHDL - [expand]
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signal input_10ms : unsigned(N-1 downto 0);
 
input_10ms_driver : process
begin
  wait for 10 ms;
  wait until rising_edge(sys_clk);    -- align with clock
  input_10ms <= input_10ms + 1;
end process;

---

;

 

[ads-ee]

Instead of giving the simulator lots of work to do with a system clock counter, why not just do this:

---

Code VHDL - [expand]
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signal input_10ms : unsigned(N-1 downto 0);
 
input_10ms_driver : process
begin
  wait for 10 ms;
  wait until rising_edge(sys_clk);    -- align with clock
  input_10ms <= input_10ms + 1;
end process;

---

;

That was my first suggestion, but I notice now that I mistakenly read the 10 ms as 1 ms.

 

[Vijay Vinay]

Hello,
I am right now trying to implement each corner case (testing for each input) in my testbench file. My code actually need to increment the values of fstep_i and fmcw_bw_i after certain time interval. And once these values are incremented, temp_s should check for the condition and should perform either up-counting or down-counting. But what happens is that fstep_i and fmcw_bw_in are incremented as per the process, whereas temp_s is always performing up-counting. I need to perform down-counting operation as well based on the condition.The vhdl code is as follows.

begin
  p_fmcw : process(reset_n_i, clk_128m_i)
  begin
    if (reset_n_i = '0') then
      temp_s <= 0;
      cnt_s <= '0';
    elsif (clk_128m_i'event and clk_128m_i = '1') then
      if (enable_i = '1' and fmcw_trig_i = '1') then
        if (temp_s = 0) then
	  temp_s <= temp_s + to_integer(unsigned(fstep_i));   -- Accumulated values of temp_s and fstep_i
	  cnt_s <= '0';
	elsif (temp_s >= (to_integer(unsigned(fmcw_bw_i)))) then
	  temp_s <= temp_s - to_integer(unsigned(fstep_i));
	  cnt_s <= '1';
	elsif (cnt_s = '0') then
	  temp_s <= temp_s + to_integer(unsigned(fstep_i));   -- Up counter
	else
	  temp_s <= temp_s - to_integer(unsigned(fstep_i));   -- Down counter
	end if;
      else
       temp_s <= 0;
       cnt_s <= '0';
      end if;
    end if;
  end process;

  fmcw_ramp_o <= std_logic_vector(to_unsigned(temp_s,24));
end rtl;

temp_s is an integer ranging from 0 to 16777215.

The testbench file looks like this:

 p_stim: process
  begin		
     
	  wait for 100 ns;
	  reset_n_i <= '0';
	 
     wait for clk_128m_i_period*10;
     reset_n_i <= '1';
	  		
     wait for clk_128m_i_period;
     enable_i <= '1';
     fmcw_trig_i <= '1';
     
     fmcw_bw_i <= "000000000000000000000000";           -- 10000
    
    
	   if (fmcw_bw_i <= "111111111111111111111110") then
		  fmcw_bw_i <= std_logic_vector(unsigned(fmcw_bw_i)+1);
		else
		  fmcw_bw_i <= (others => '0');
		end if;
	end process;  
	p_stim_n : process
   begin
     wait for 100 ns;
	  reset_n_i <= '0';
	  
	  
     wait for clk_128m_i_period*10;
     reset_n_i <= '1';
	  		
     wait for clk_128m_i_period;
     enable_i <= '1';
     fmcw_trig_i <= '1';
	  
	  fstep_i <= "0000000000";                           -- 1020		
	  fstep_i <= std_logic_vector(unsigned(fstep_i)+1);
	  
		
  end process;

When I implement this code for a single value of fstep_i and fmcw_bw_i, its working properly doing up-counting and down-counting whenever necessary. But its not working when I implement the same using this testbench file. I feel that there are some mistakes, but I don't know where. I don't have any idea of how to solve this problem. Help is appreciated.