testbed setup for INL,DNL,SNDR,FFT...

[pnanda65675]

inl dnl fft

im not quite sure abt all this testbed(cct) for testing pipeline ADC performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???

 

[sunking]

dnl setup latest version

INL and DNL: vpwl
SNDR and FFT: vsine

 

[rambus_ddr]

ind dnl script matlab

But there are all ideal componet, such no offset of opamp and comparator, resistor mismatch, is this method simulation results can meet the real performance reqirements?

 

[sankudey]

dnl and inl with verilog

I am not clear of the question....is the designed ADC/DAC is in Verilog A(or some thing like that) and only involves mathematics? ...or real deivces with their models?...if first...then obviously it will show the theoritical values (at least very close)...if made with real devices...of corce not...and you will get some variantions......

if you are worried about the process variation (for the second case)...then you can run the worst case(wcs)/bcs model files....or FF/SS etc. corner......by corner analysis you can handle with the absolute device mismatch....but...its true that device mismatch (relative) is very tough to get at simulation level....I heard people go for monte carlo simulation for the same...but its very much time consuming...thus relative device mismatch (which is very low) is taken care of at design level..then layout level...the rest contribute to bad yield...

Added after 35 seconds:

btw...what does it mean by vpwl....

 

[opamp741]

inl fft adc

vpwl stands for the piece wise linear voltage

 

[kytan]

hey Nanda,

The test setup for ADC is after you fabricated the chip then you measure those performance like INL. DNL, etc. Before you fabricate the chip i.e. in design stage you should be able to get some value for those metrics by system level simulation depending on your initial product/system design specification. This is typically done using MatLab or verilog-a so when you finally finish and tape out you can compare the ideal results and the real results.

KY Tan