Test Scenarios of DDR2 controller

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sumathi0809

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Please anybody tell me, what will be the "test scenarios for verification of DDR2 controller"..?
 

1)DDR initialization
2)Memory writes and reads
3)Scenario 2) for different combinations of rows, columns and banks
4)Power down(Both precharge and active)
5)Refresh operation
 
Thank you for your reply, if possible can u tell me how to verify refresh, controller-PHY will automatically performs refresh operation do i have to poll for PHY refresh command to memory at periodic intervals..?
 

If there is a refresh violation, the memory model itself throws out an error and the simulation stops. But it will not warn you if the time is in excess. Use a simulator to determine the exact delay and refer the memory datasheet to confirm the same.
 

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