please help me
for test point insertion below flow is correct or not ?
1--take rtl and do functionl verification......input=rtl,tb output=functional simulation out put file
2--take the rtl into dft compiler run with required constraints & generate un mapped netlist ........input=rtl,library ,,,output=unmapprd netlist
3--insert dft (define ports)
4--generate scan ready netlist......input=unmapped netlist, output=scan ready netlist
5--generate scan stitched netlist........input=scan ready netlist, output=scan stitched netlist
6--create test protocol file
7-- do physical design implementation up to routing.....input to ic compiler=scan stitched netlist, output=routed scan stitched netlist
8--the routed scan stitched netlist, simulation library & protocol file are taken into tetramax.....i/p=routed scan stitched netlist,library,protocol file
9--do simulation, & fault simulation (doubt ::::how to do simulation and fault simulation and how we will compare)
10--find the undetected faults
11--find location of undetectable faults
12--analyze the results
13--for inserting user defined test points go to dft compiler (doubt::::::where we need to go step 2 or 3 or 4 or 5 or 6 or 7)
14--insert the test points
15--repeat the step 5 to step 12
is the flow is correct
and what are the inputs and outputs at each stage.