test if set in vhdl different implementation

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ghattasak

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if i have a array of 0 to M ot std_logic in vhdl and i want to test if it is set having all bits 1, is it advised to use "and gate" or should i use an if statement. what is the difference in hardware?
 

And gates is like a mask, more quick than an if statement.
 

it will cost me more hardware right ? if i have lets say an array of 1000
 

Yes, in these cases it's more straightforward to mask bit a bit than an recursive if statement.
 

an if statement that just does an equality:

if a = "1111" then do something;

will probably just create an and gate anyway. and its easier to read. Unless you have some really old device where LUT count is important, readible code is better than smaller implementation.

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if you want to just and all the bits, there is the and_reduce function in the std_logic_misc library:

op <= and_reduce(ip);

or if you have 2008 support:

op <= and ip;
 
Do that: try coding both implementations and then look at the synthetized blocks, it's more easy than just try to guess how it's implemented in hardware by the compiler.
 
done_sort <= '1' when done_arr =((others => '1')) else '0';

can i write it like this ? supposedly done_arr is an array of 0 to M and i want it to varry depending on M and not set up like a 1000 1's

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@TrickyDicky
i am using the and_reduce now to check for the results
thank you

@rusty81
yes i will implement them but i might lose track in a big design implementation
thank you
 

ghattasak said:
done_sort <= '1' when done_arr =((others => '1')) else '0';

can i write it like this ? supposedly done_arr is an array of 0 to M and i want it to varry depending on M and not set up like a 1000 1's
Click to expand...
No, "others" can only be used in an assignment.
You can create a constant with all ones to be used in the compare:

Code VHDL - [expand]
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constant all_ones : std_logic_vector(0 to M) := (others => '1');
 
...
 
done_sort <= '1' when done_arr = all_ones else '0';
 

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