[SOLVED] test bench waveform display

hi....
for simulating my project i created a test bench using ise 14.3 .. but when the behavioral model is run only waveforms upto 500ps are displayed. the clk period is 1ns. how can i increase the time for which waveform is displayed?

Hi there,
i simulate menu choose start simulation and in the opened window change resolution from default to ps

hi sir,
it was the problem with my code. was not entering the loop. So i modified the code but it doesnt produced any delay. i think the problem is that the signal mask is always having a value 'U'. can you pls help me in finding the error. i tried alot but it was not fruitful. the code which i wrote is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_try is
Port ( clk : in STD_LOGIC;
mask : inout STD_LOGIC;
a : out STD_LOGIC;
b : out STD_LOGIC_VECTOR (2 downto 0);
c : inout STD_LOGIC_VECTOR (2 downto 0));
end delay_try;

architecture delay_try_beh of delay_try is
signal flag:bit;
signal counta:integer;
signal countb:integer;
begin
process(clk)
begin
if clk='1' and clk'event then
if flag='0' then
counta<=counta+1;
if counta=10 then
flag<='1';
end if;
end if;
if flag='1' then
counta<=counta-1;
if counta=0 then
flag<='0';
end if;
end if;
end if;
end process;
process(clk,flag)
begin
a<='1';
c<="101";
if flag='1' and flag'event then
if mask='0' then
countb<=countb+1;
if countb=10 then
mask<='1';
end if;
else null;
end if;
end if;
a<='0';
b<=c;
end process;
end delay_try_beh;

test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dly_mdl IS
END dly_mdl;

ARCHITECTURE behavior OF dly_mdl IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT delay_try
PORT(
clk : IN std_logic;
mask : INOUT std_logic;
a : OUT std_logic;
b : OUT std_logic_vector(2 downto 0);
c : INOUT std_logic_vector(2 downto 0)
);
END COMPONENT;


--Inputs
signal clk : std_logic := '0';

--BiDirs
signal mask : std_logic;
signal c : std_logic_vector(2 downto 0);

--Outputs
signal a : std_logic;
signal b : std_logic_vector(2 downto 0);

-- Clock period definitions
constant clk_period : time := 1 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: delay_try PORT MAP (
clk => clk,
mask => mask,
a => a,
b => b,
c => c
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- c<="111";
mask<='0';
wait for 200 ns;
-- insert stimulus here
wait;
end process;

END;

are you running the testbench or the entity? you need to run the testbench.

Also, why is mask an Inout? in the testbench there is no code for handling the tri-state driver.

i ran behavioral simulation by selecting the test bench. mask is declared as inout as i am reading as well as writing value to it. first i assigned value to mask within the second process but error was displayed when i synthesized it saying "its a bad assignment". thatsy i wrote its value in test bench. but no error was displayed why i simulated test bench. why it is so? if it is unsupported it should be displayed as an error during simulation na.

you should only use inout for external tri-states. Because you have no tri-state control the error will be because of multiple assignements to mask. If you just intend for the value to be read back from inside then declare mask as "buffer" instead of inout. Otheriwse you should consider separate in and out signals.

k. let me try. thanks alot

hi....
the problem is solved. it was a problem with my code. i replaced the loop statements with if construct. then it worked. the problem was whenever positive clock edge comes the program terminates. also i learned that you can change the time for which waveform is displayed by right clicking on behavioral simulation and suitably adjusting the time.. thanks to everyone for their suggestions...