module ringosc (clkout);
output clkout;
parameter NUMGATES = 3;
(* keep="true" *)
wire [NUMGATES-1:0] patch;
generate
genvar i;
for (i = 0; i < NUMGATES-1; i = i + 1)
begin: for_gates
(* keep="true" *)
assign patch[i+1] = ~patch;
end
endgenerate
(* keep="true" *)
assign patch[0] = ~patch[NUMGATES-1];
// Plain output
assign clkout = patch[0];
endmodule
module trng_wrapper (clk, resetn, random_num);
input clk;
input resetn;
output reg [127:0] random_num;
parameter NUMRO_TRNG = 10;
wire random_bit;
wire [NUMRO_TRNG-1:0] ind_ro_output;
always @ (posedge clk or negedge resetn)
if (!resetn)
random_num <= 128'h0;
else
random_num <= {random_num[126:0], random_bit};
generate
genvar i;
for (i = 0; i < NUMRO_TRNG; i = i + 1)
begin: Ring_Osc
ringosc RO (ind_ro_output);
end
endgenerate
assign random_bit = ^ind_ro_output;
endmodule