Test bench code error in VHDL

Code VHDL - [expand]
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ENTITY filter_tb IS
END filter_tb;
 
ARCHITECTURE behavior OF filter_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fir_4tap
    PORT(
         Clk : IN  std_logic;
         Xin : IN  std_logic_vector(7 downto 0);
         Yout : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal Clk : std_logic := '0';
   signal Xin : std_logic_vector(7 downto 0) := (others => '0');
 
    --Outputs
   signal Yout : std_logic_vector(15 downto 0);
 
   -- Clock period definitions
   constant Clk_period : time := 20 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: fir_4tap PORT MAP (
          Clk => Clk,
          Xin => Xin,
          Yout => Yout
        );
 
   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
 
      wait for Clk_period*10;
 
      -- insert stimulus here 
 
      wait;
   end process;
    
      monitor : PROCESS (clk)
  variable c_str : line;
  begin
    if (clk = '1' and clk'event) then
      write(c_str,Yout);
      assert false report time'image(now) & 
        ": Current Count Value : " & c_str.all
      severity note;
      deallocate(c_str);
    end if;
  end PROCESS monitor;
 
END;