Test bench clock gen problem

barry said:

The way I would do this is generate a free-running clock and then use the sclk_en to enable a second process that would generate your sclk.

Click to expand...

                   sclk_process :process
                   begin			
			sclk1 <= '0';
			wait for sclk_period/2;
			sclk1 <= '1';
			wait for sclk_period/2;		
                   end process;
	
	          sclk_en_process :process(sclk_en)
                  begin	
		     if (sclk_en='1') then
			sclk<=sclk1;
		     else
			sclk<='1';		
		     end if;
                   end process;

hithesh123 said:

How do you do this?

Here's what I tried and it didn't work -

Code:

                   sclk_process :process
                   begin			
			sclk1 <= '0';
			wait for sclk_period/2;
			sclk1 <= '1';
			wait for sclk_period/2;		
                   end process;
	
	          sclk_en_process :process(sclk_en)
                  begin	
		     if (sclk_en='1') then
			sclk<=sclk1;
		     else
			sclk<='1';		
		     end if;
                   end process;

- - - Updated - - -

ok, got it.
Just had to add sclk and sclk1 to the process sensitivity list.

Do you do it the same way?

Click to expand...

barry said:

I generally like to have everything synchronous, i.e., every process has a clock. What you've got will probably work fine for a testbench, but keep in mind that what you've generated is a "gated clock" which are generally avoided. This means that it is susceptible to glitches, for one thing.

Click to expand...

process(sclk1)
begin
  if rising_edge(sclk1) then
    some_en <= not some_en;
  end if;
end process;

process(sclk)
begin
  if rising_edge(sclk) then
    if some_en = '1' then
      --do something
      --When you look at the waveform, it may look like something happens when some_en = '0'
    end if;
  end if;
end process;