Test bench and verification of code

Status
Not open for further replies.
H

hassan590

Newbie level 3
Joined
Sep 17, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
37
I am new in VHDL. I wrote a code of decrement counter in which counter picks integer from the array and counts it down to zero and increments the check output. I want you guys to verify if the code is logically correct. If yes then how can i test it using the test bench.

Code: 
entity counter is
port(clk :in bit;
check : out integer);
end counter;     

architecture imp of counter is
type my_array is array(natural range<>) of integer;
constant set:my_array(1 to 5):= (2,4,6,8,10);--array of 5 integers
signal count:integer:=set(1); --initiating count with integer at first location of array 
signal t : integer;
begin
process(clk)
variable i : integer:= 1;--to be used to indicate the locations of array 
begin
if (clk='1' and clk'event) and (count>0) then
count<=count-1;
elsif (clk='1' and clk'event) and (i<5) then 
i:=i+1;
count<= set(i);
t<=t+1;
end if;
end process;
check<=t;
end imp;
 

I think you need to read a book on logic design.

Code: 
if (clk='1' and clk'event) and (count>0) then
along with an else clause of
Code: 
elsif (clk='1' and clk'event) and (i<5) then
That's a gated clock with the gating signal two different compare operations. :-(

I guarantee a sythesis tool will choke on that if statement you wrote.

I wouldn't design a gated clock circuit into an FPGA unless I knew exactly how I was going to place every logic cell and ensure I wouldn't have issues with glitch pulses (which your design is guaranteed to have). You will likely run a simulation and think everything is great but you would have to run a back annotated four corner timing simulation to really determine if that was the case.

The use of a variable seems to be a favorite past time among the SW oriented VHDL newbies (who think VHDL code is just like a SW program). I would recommend against using it unless you really understand what it translates into HW in all use cases. I'm somewhat surprised that you didn't resort to a for loop to cycle through the i values, as that's what those familiar with SW resort to using, but fail to realize they just created "N" copies of logic within the loop.

To put it mildly your code should be rewritten and would very likely choke in synthesis and in simulation.

Regards
 


Why would you expect someone else to do your work? You can obviously write VHDL code, a testbench is simply more VHDL code. What exactly do you need help with in writing? All you do in the testbench is
- Instantiate your entity that is to be tested
- Write models for each of the input signals
- Write code that checks the outputs

In a testbench you are not constrained by synthesis rules so you are free to write things like this...
...
wait until rising_edge(clk);
assert check = '0' report "OOPS! Check is not correct" severity ERROR;
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
assert check = '1' report "OOPS! Check is not correct" severity ERROR;
wait; -- All done, wait forever
...

You'll also want to break up your 'if' statement. For synthesizable code the if needs to be looking for nothing more than simply the rising (or falling...but not both) edge of the clock. Any other checking needs to be embedded within another if statement like this...
...
Code: 
if rising_edge(clk) then
   if (a > 5) then
      ...
   end if;
end if;

Kevin Jennings
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…