Tessent MBIST for memories with dedicated test clock

[Sergoi]

Hi folks.
I have single port memory with a dedicated test clock port, i.e. in *.lvlib for clock port:

Port (CLK)
        {
            Direction: INPUT;
            Function: Clock;
            Plarity: ActiveHigh;
            EmbeddedTestLogic {
                TestInput: TCLK;
            }
        }

there are also select for CLK/TCLK in *.lvlib

Port (TCLKE)
{
    Direction: INPUT;
    Polarity: ActigeHigh;
    Function: BistEn;
}

Moreover, separate test clock port (MBIST_CLK) must be present in design, i.e. it is impossible to use functional clock(FUNC_CLK) for mbist. Required mbist config is like this (without memory interfaces/collars for simplicity):

I'm using tshell, not LV. So, i'm add_clock to 'TCLK' and add_dft_clock_mux for 'CLK' 'TCLK' with 'all_test' as a dft control signal. But at the check_design_rule stage i have a DFT_C1-1 error "Memory clock not properly sourced by a declared clock". Aslo i'v tried to use add_dft_control_points and other ways, like add single pseudo port for both CLK and TCLK, to solve this problem, but it's all fails, DFT_C1-1 error staying.
Does anyone knows how to use separate test mbist clock for testing memories with internal mux on clock port?

 

[rca]

why functional clk need to be define?
I never used a memory with a dedicated test clock port, I do not understand why the tool should force you for that.

 

[Sergoi]

Thanks for answer.
Tool doesn't, but memory compiler does.
Memories with dedicated test clock also have all other test logic inside. For such memories Tessent tool doesn't place collar and other test logic. So, this makes possible to reduce test logic in all.

 

[vipul982]

Going by details provided by tessent and your lvlib snippet, this memory has internal muxing logic to select functional clock or bist clock. You should be good by defining only MBIST_CLK, mux select line is already controlled by BistEn. I'm assuming that internal muxing is there to gate functional clock in mbist mode and control power dissipation.

Edit1:
1 suggestion I have is to try adding default value of "1" for TCLKE port in your lvlib port definition if you still see a problem.

 

[hiblet]

You can learn how to define test inputs, functional inputs, and what should already exist in the design by searching for "EmbeddedTestLogic" in the Tessent™ MemoryBIST User’s Manual.

 

[Sergoi]

Thanks.
Of course, I'v learned the "Tessent Core Description" format well. But the problem not in *.tcd description of memory.
When the tool have connection and driving ability for "EmbeddedTestLogic" ports TCLK and TCLKE, tool also wants a clock on a functional port CLK. But it's not matter what on CLK port, because thorugh TCLKE port tool already control clock signal from which port: CLK or TCLK goes inside memory core. Because for testing purposes TCLKE clock is nedeed, it is not necessary to have a clock on the CLK. But the tool does not allow it. Tool wants CLK clock too.
The question is how to declare only TCLK clock, without of declaration of CLK?

 

[maulin sheth]

Thanks.
Of course, I'v learned the "Tessent Core Description" format well. But the problem not in *.tcd description of memory.
When the tool have connection and driving ability for "EmbeddedTestLogic" ports TCLK and TCLKE, tool also wants a clock on a functional port CLK. But it's not matter what on CLK port, because thorugh TCLKE port tool already control clock signal from which port: CLK or TCLK goes inside memory core. Because for testing purposes TCLKE clock is nedeed, it is not necessary to have a clock on the CLK. But the tool does not allow it. Tool wants CLK clock too.
The question is how to declare only TCLK clock, without of declaration of CLK?

Why do you need to define the add_clock TCLK? Is it a port in your design?

 

[Sergoi]

Why do you need to define the add_clock TCLK? Is it a port in your design?

TCLK is one of the ports of my memory. Each memory have port CLK - functional clock, and port TCLK - mbist clock. Port TCLKE is a selector between these two clocks.
My tessent flow looks like:

1. create "mbist_clock" port on the top level. Apply add_clocks command to " mbist_clock" port i.e. declare mbist test clock on this port
2. create connection between port "mbist_clock" and memory port "TCLK"
3. ...
4. check_design_rules

tshell gives an error message to memory port "CLK": "DFT_C1-1 error "Memory clock not properly sourced by a declared clock"". According to my understanding, it's not matter what on memory port "CLK", cause memory test clock port is "TCLK", and we have a clock on this port. But tool thinks otherwise.

To resolve this problem i tried to explain to the tool, that there is multiplexer inside memory:

1. Apply command "add_clocks" to memory port "TCLK"
   
2. Apply command "add_dft_clock_mux" with arguments memory port "TCLK", memory port "CLK" and "all_test" signal as a select.
   
3. ...
4. check_design_rules

And tshell again give me an error "DFT_C1-1 error "Memory clock not properly sourced by a declared clock""