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| // testbench here
// or browse Examples
// fill 20 pos (write)
// fork
// read // 10 pop -- 12
// write // 12 push -- 10
// join
// compare - fifo size - (32)full/(0)empty signal
// bit[31:0] queue[$];
//
// queue.push_back(item)
// queue.pop_front(item)
// queue = {}; queue.size() == 0 /32
module fifo_top_tb;
reg wr_clk,rd_clk;
reg[31:0] data_in;
wire[31:0] data_out;
wire rd_empty,wr_full;
reg reset_w;
reg reset_r;
reg write_enable,read_enable;
fifo_top top1(.wdata(data_in),
.rdata(data_out),
.wclk(wr_clk),
.rclk(rd_clk),
.wreset_b(reset_w),
.rreset_b(reset_r),
.write(write_enable) ,
.read(read_enable),
.rempty(rd_empty),
.wfull(wr_full));
bit[31:0] queue[$];
int i,j;
reg count;
reg queue_size;
task initilize;
begin
write_enable =0;
read_enable =0;
wr_clk=0;
rd_clk=0;
data_in=0;
$monitor ("wr_clk=%d,reset_w=%d,reset_r=%d,write_enable=%d,read_enable=%d,data_in=%d,data_out=%d,wr_full=%d,rd_empty=%d"
,wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty);
end
endtask
task wrreset;
begin
reset_w=0; // asserted
data_in=0;
write_enable =0;
read_enable =0;
end
#10 reset_w =~reset_w;
endtask
task write(input w,r,
input [4:0]no_of_times);
reg [4:0] h;
begin
for(h = 0;h<=no_of_times;h=h+1)
begin
#10
@(posedge wr_clk)
data_in = $random;
write_enable=w;
read_enable=r;
end
end
endtask
task writeread(input w,r,
input [4:0] no_of_times);
begin
write(w,r,no_of_times);
read(w,r,no_of_times);
end
endtask
initial
wr_clk=0;
always
#20wr_clk= ~wr_clk;
initial
begin
wrreset;
initilize;
write(1,0,20);
$display($time,"write operation is over \n");
//#10read(0,1,15);
#100 $finish ;
end
task rdreset;
begin
reset_r=0; //asserted
#10 reset_r=~reset_r;
end
endtask
task read(input w,r,
input [4:0]no_of_times);
reg[4:0] h;
begin
$display($time,"COntrol has entered the loop ");
for(h = 0;h<=no_of_times;h=h+1)
begin
@(posedge rd_clk)
begin
write_enable=w;
read_enable=r;
end
end
end
#10 reset_r=~reset_r;
endtask
initial
begin
rdreset;
initilize;
/*write(1,0,15);*/
read(0,1,20);
$display($time,"read operation is over \n");
#100 $finish ;
end
initial
rd_clk=0;
always
#20 rd_clk= ~rd_clk;
initial
begin
$dumpfile("fifo_top_tb.vcd");
$dumpvars(wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty);
end
initial #2$monitor("wr_clk=%d,reset_w=%d,reset_r=%d,write_enable=%d,read_enable=%d,data_in=%d,data_out=%d,wr_full=%d,rd_empty=%d"
,wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty);
initial #800$finish;
initial
fork
for(i=0;i<=12;i=i+1)
begin
queue.push_back(data_in[i]);
$display("queue[i]=%p",queue[i]);
end
for(j=0;j<=10;j=j+1)
begin
queue.pop_front();
$display("queue[j]=%p",queue[j]);
end
join
always @(posedge wr_clk )
begin
if (reset_w )
begin
count = 0; end
else if(count!=32 && write_enable)
begin
count=count +1;
end
else
begin
count=count;
end
end
//READ
always @(posedge rd_clk)
begin
if(reset_r)
begin
count=32;
end
else if (count!=0 && read_enable)
begin
count=count-1;
end
// Concurrent read and write.. no change in count
else
begin
count = count;
end
end
// *** Update the flags
//
// First, update the empty flag.
//
always @(count)
begin
if(queue_size==32)
begin
$display("full");
end
end
// Update the full flag
//
always @(count)
begin
if(queue_size==0)
begin
$display("empty");
end
else
begin
$display("neither full nor empty");
end
end
initial
begin
$dumpfile("fifo_top_tb.vcd");
$dumpvars(1,data_in,data_out,wr_clk,rd_clk,wr_full,rd_empty);
end
endmodule
//Design here
module fifo_top
#(
parameter DEPTH = 32,
WIDTH = 32,
ADDR = 5
)
(
input wire write, wreset_b, wclk, read, rreset_b, rclk,
input wire [WIDTH-1:0] wdata,
output wire [WIDTH-1:0] rdata,
output wire rempty, wfull
);
// function to convert from gray to binary
function [ADDR:0] G2B_Fn;
input [ADDR:0] gray;
reg [ADDR:0] binary;
integer i;
begin
binary[ADDR] = gray [ADDR];
for (i=ADDR-1;i >= 0;i=i-1)
binary[i] = (binary[i+1] ^ gray[i]);
G2B_Fn = binary;
end
endfunction
// declare connecting wires
wire [ADDR:0] wptr_b,wptr_g, // binary and gray signals from write pointer
rptr_b,rptr_g; // binary and gray signals from read pointer
reg [ADDR:0] g2b_wd_op, // function G2B_Fn output in the write domain
g2b_rd_op; // function G2B_Fn output in the read domain
wire [ADDR:0] g2b_wd_ip, // function G2B_Fn input in the write domain
g2b_rd_ip; // function G2B_Fn input in the read domain
//assign intermediate wires
always @(g2b_wd_ip or g2b_rd_ip)
begin
g2b_wd_op = G2B_Fn(g2b_wd_ip);
g2b_rd_op = G2B_Fn(g2b_rd_ip);
end
// instantiate write pointer
pointer wptr(
.clk(wclk),
.reset_b(wreset_b),
.op(write),
.fifo_status(wfull),
.gray(wptr_g),
.binary(wptr_b)
);
//instantiate read pointer
pointer rptr(
.clk(rclk),
.reset_b(rreset_b),
.op(read),
.fifo_status(rempty),
.gray(rptr_g),
.binary(rptr_b)
);
//instantiate memory module
memory m1(
.clk(wclk),
.reset_b(wreset_b),
.write(write),
.wfull(wfull),
.waddr(wptr_b[ADDR-1:0]),
.raddr(rptr_b[ADDR-1:0]),
.wdata(wdata),
.rdata(rdata)
);
//instantiate read->write synchronizer
sync_r2w syncr2w(
.clk(wclk),
.reset_b(wreset_b),
.rptr(rptr_g),
.rptr_wr(g2b_wd_ip)
);
//instantiate write->read synchronizer
sync_w2r syncw2r(
.clk(rclk),
.reset_b(rreset_b),
.wptr(wptr_g),
.wptr_rd(g2b_rd_ip)
);
//instantiate write domain comparator
compare_wr cmp_wr(
.rptr(g2b_wd_op),
.wptr(wptr_b),
.full(wfull)
);
//instantiate write domain comparator
compare_rd cmp_rd(
.rptr(rptr_b),
.wptr(g2b_rd_op),
.empty(rempty)
);
endmodule
module pointer
#(
parameter ADDR = 5 // parameterized size of pointers
)
(
input wire clk,reset_b,op,fifo_status, // input-output declaration
output reg [ADDR:0] gray,binary
);
integer i;
always@(posedge clk, negedge reset_b)
begin
if(~reset_b)
begin
binary = 'd0;
gray = 'd0;
end
else if(op & ~fifo_status)
binary <= binary + 1;
end
always @(binary)
begin
gray[ADDR] = binary[ADDR];
for (i=ADDR-1;i>=0;i=i-1)
gray[i] = binary[i] ^ binary[i+1];
end
endmodule
module memory
#(
parameter DEPTH = 32, // parameter declaration
WIDTH = 32,
ADDR = 5
)
(
input wire clk, reset_b, write, wfull, // input - output declaration
input wire [ADDR-1:0] waddr, raddr,
input wire [WIDTH-1:0] wdata,
output wire [WIDTH-1:0] rdata
);
integer i;
// creating memory
reg [WIDTH-1:0] sram [DEPTH-1:0];
// writing in the memory
always @(posedge clk, negedge reset_b)
begin
if(~reset_b)
begin
for(i=0;i<DEPTH;i = i+1)
sram[i] <= 'h0;
end
else if(write & ~wfull)
sram[waddr] <= wdata;
end
// reading a memory location
assign rdata = sram[raddr];
endmodule
// to synchronize from fast clock domain to slow clock domain (write -> read)
module sync_w2r
#(
parameter ADDR = 5
)
(
input wire clk, reset_b,
input wire [ADDR:0] wptr,
output reg [ADDR:0] wptr_rd
);
reg [ADDR:0] q;
always @(posedge clk or negedge reset_b)
begin
if(~reset_b)
begin
q <= 'd0;
wptr_rd <= 'd0;
end
else
begin
q <= wptr;
wptr_rd <= q;
end
end
endmodule
// to synchronize from slow clock domain to fast clock domain (read -> write)
module sync_r2w
#(
parameter ADDR = 5
)
(
input wire clk, reset_b,
input wire [ADDR:0] rptr,
output reg [ADDR:0] rptr_wr
);
reg [ADDR:0] q;
always @(posedge clk or negedge reset_b)
begin
if(~reset_b)
begin
q <= 'd0;
rptr_wr <= 'd0;
end
else
begin
q <= rptr;
rptr_wr <= q;
end
end
endmodule
module compare_wr
#(
parameter ADDR = 5 // declare parameter for memory address
)
(
input wire [ADDR:0] rptr,wptr, // declare inputs and outputs
output wire full
);
//check for full condition: Write pointer has wrapped around but read pointer has not
assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]);
endmodule
module compare_rd
#(
parameter ADDR = 5 // declare parameter for memory address
)
(
input wire [ADDR:0] rptr,wptr, // declare inputs and outputs
output wire empty
);
//check for full condition: WRITE and READ pointers have NOT wrapped around
assign empty = wptr[ADDR:0] == rptr[ADDR:0];
endmodule |